Question 1 |

Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?

P is 10:1 multiplexer; Q is 5:1 multiplexer; T is 2:1 multiplexer | |

P is 10:2^{10} decoder; Q is 5:2^{5} decoder; T is 2:1 encoder | |

P is 10:2^{10} decoder; Q is 5:2^{5} decoder; T is 2:1 multiplexer | |

P is 1:10 de-multiplexer; Q is 1:5 de-multiplexer; T is 2:1 multiplexer |

Question 1 Explanation:

Question 2 |

Micro program is:

the name of a source program in micro computers | |

set of microinstructions that defines the individual operations in response to a machine-language instruction | |

a primitive form of macros used in assembly language programming | |

a very small segment of machine code |

Question 2 Explanation:

Question 3 |

Consider a main memory system that consists of 8 memory modules attached to the system
bus, which is one word wide. When a write request is made, the bus is occupied for 100
nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for
500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________

5000 | |

10000 | |

2000 | |

8000 |

Question 3 Explanation:

Question 4 |

Two control signals in microprocessor which are related to Direct Memory Access (DMA) are

INTR & INTA | |

RD & WR | |

S0 & S1 | |

HOLD & HLDA |

Question 4 Explanation:

Question 5 |

The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields. a micro operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

10, 3, 1024 | |

8, 5, 256 | |

5, 8, 2048 | |

10, 3, 512 |

Question 5 Explanation:

Question 6 |

Consider a CPU where all the instructions require 7 clock cycles to complete execution. There are 140 instructions in the instruction set. It is found that 125 control signals are needed to be generated by the control unit. While designing the horizontal microprogrammed control unit, single address field format is used for branch control logic. What is the minimum size of the control word and control address register?

125, 7 | |

125, 10 | |

135, 9 | |

135, 10 |

Question 6 Explanation:

Question 7 |

The data path shown in the figure computes the number of 1s in the 32-bit input word corresponding to an unsigned even integer stored in the shift register.

The unsigned counter, initially zero, is incremented if the most significant bit of the shift register is 1.

The microprogram for the control is shown in the table below with missing control words for microinstructions I_1, I_2, \ldots I_n.

\begin{array}{|l|c|c|c|} \hline \textbf {Microinstruction} & \textbf{Reset Counter}& \textbf{Shift left} & \textbf{Load output} \\\hline \text{BEGIN} & \text{1} & \text{0} & \text{0} \\\hline \text{I1}& \text{$?$} & \text{$?$} & \text{$?$} \\\hline \text{:} & \text{:} & \text{:} & \text{:} \\\hline \text{In} & \text{$?$} & \text{$?$} & \text{$?$} \\\hline \text{END} & \text{0} & \text{0} & \text{1} \\\hline \end{array}

The counter width (k), the number of missing microinstructions (n), and the control word for microinstructions I_1, I_2, \ldots I_n are, respectively,

The unsigned counter, initially zero, is incremented if the most significant bit of the shift register is 1.

The microprogram for the control is shown in the table below with missing control words for microinstructions I_1, I_2, \ldots I_n.

\begin{array}{|l|c|c|c|} \hline \textbf {Microinstruction} & \textbf{Reset Counter}& \textbf{Shift left} & \textbf{Load output} \\\hline \text{BEGIN} & \text{1} & \text{0} & \text{0} \\\hline \text{I1}& \text{$?$} & \text{$?$} & \text{$?$} \\\hline \text{:} & \text{:} & \text{:} & \text{:} \\\hline \text{In} & \text{$?$} & \text{$?$} & \text{$?$} \\\hline \text{END} & \text{0} & \text{0} & \text{1} \\\hline \end{array}

The counter width (k), the number of missing microinstructions (n), and the control word for microinstructions I_1, I_2, \ldots I_n are, respectively,

32,5,010 | |

5,32,010 | |

5,31,011 | |

5,31,010 |

Question 7 Explanation:

Question 8 |

An instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive signals as follows:

Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals.

How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming?

Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals.

How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming?

0 | |

103 | |

22 | |

55 |

Question 8 Explanation:

Question 9 |

A hardwired CPU uses 10 control signals S_1 to S_{10}, in various time steps T_1 to T_5, to implement 4 instructions I_1 to I_4 as shown below:

\begin{array}{|c|c|c|c|c|c|}\hline&\bf{T_1}&\bf{T_2}&\bf{T_3}&\bf{T_4}&\bf{T_5}\\\hline\bf{I_1}&S_1,S_3,S_5&S_2,S_4,S_6&S_1,S_7&S_{10}&S_3,S_8\\\hline\bf{I_2}&S_1,S_3,S_5&S_8,S_9,S_{10}&S_5,S_6S_7&S_{6}&S_{10}\\\hline\bf{I_3}&S_1,S_3,S_5&S_7,S_8,S_{10}&S_2,S_6,S_{9}&S_{10}&S_1,S_3\\\hline\bf{I_4}&S_1,S_3,S_5&S_2,S_6,S_7&S_5,S_{10}&S_{6},S_9&S_{10}\\\hline\end{array}

Which of the following pairs of expressions represent the circuit for generating control signals S_5 and S_{10} respectively?

((I_j + I_k)T_n indicates that the control signal should be generated in time step T_n if the instruction being executed is l_j or l_k)

\begin{array}{|c|c|c|c|c|c|}\hline&\bf{T_1}&\bf{T_2}&\bf{T_3}&\bf{T_4}&\bf{T_5}\\\hline\bf{I_1}&S_1,S_3,S_5&S_2,S_4,S_6&S_1,S_7&S_{10}&S_3,S_8\\\hline\bf{I_2}&S_1,S_3,S_5&S_8,S_9,S_{10}&S_5,S_6S_7&S_{6}&S_{10}\\\hline\bf{I_3}&S_1,S_3,S_5&S_7,S_8,S_{10}&S_2,S_6,S_{9}&S_{10}&S_1,S_3\\\hline\bf{I_4}&S_1,S_3,S_5&S_2,S_6,S_7&S_5,S_{10}&S_{6},S_9&S_{10}\\\hline\end{array}

Which of the following pairs of expressions represent the circuit for generating control signals S_5 and S_{10} respectively?

((I_j + I_k)T_n indicates that the control signal should be generated in time step T_n if the instruction being executed is l_j or l_k)

S_5 = T_1 + I_2 \cdot T_3 and S_{10} = (I_1 + I_3) \cdot T_4 + (I_2 + I_4) \cdot T_5 | |

S_5 = T_1 + (I_2 + I_4) \cdot T_3 and S_{10} = (I_1 + I_3) \cdot T_4 + (I_2 + I_4) \cdot T_5 | |

S_5 = T_1 + (I_2 + I_4) \cdot T_3 and S_{10} = (I_2 + I_3 + I_4) \cdot T_2 + (I_1 + I_3) \cdot T_4 + (I_2 + I_4) \cdot T_5 | |

S_5 = T_1 + (I_2 + I_4) \cdot T_3 and S_{10} = (I_2 + I_3) \cdot T_2 + I_4 \cdot T_3 + (I_1 + I_3) \cdot T_4 + (I_2 + I_4) \cdot T_5 |

Question 9 Explanation:

Question 10 |

Consider the following data path of a CPU.

ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

```
Rn < = PC + 1;
PC < = M[PC];
```

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:2 | |

3 | |

4 | |

5 |

Question 10 Explanation:

There are 10 questions to complete.

Qes no.12 ( I1 IS WRITTEN 2 TIME PLEASE CORRECT (I1,I2,I3) );

Thank You devendra,

We have updated the question.