# Cache Memory

 Question 1
Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?
MSQ
 A Every access to S is a hit. B Once P is brought to the cache it is never evicted. C At the end of the execution only R and S reside in the cache. D Every access to R evicts Q from the cache.
GATE CSE 2022   Computer Organization
Question 1 Explanation:
 Question 2
A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access latency to 15 ns, whereas the miss penalty is not affected. The minimum hit rate (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is _____.
 A 0.92 B 0.88 C 0.76 D 0.85
GATE CSE 2022   Computer Organization
Question 2 Explanation:
 Question 3
Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?
MSQ
 A Each cache block in WB and WT has a dirty bit. B Every write hit in WB leads to a data transfer from cache to main memory. C Eviction of a block from WT will not lead to data transfer from cache to main memory. D A read miss in WB will never lead to eviction of a dirty block from WB.
GATE CSE 2022   Computer Organization
Question 3 Explanation:
 Question 4
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

S1: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2
S2: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct?
 A S1 is true and S2 is false B S1 is false and S2 is true C S1 is true and S2 is true D S1 is false and S2 is false
GATE CSE 2021 SET-2   Computer Organization
Question 4 Explanation:
 Question 5
Consider a set-associative cache of size 2KB ($1KB=2^{10}$ bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32 -bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is ______
 A 2 B 4 C 8 D 16
GATE CSE 2021 SET-2   Computer Organization
Question 5 Explanation:
 Question 6
Consider a computer system with a byte-addressable primary memory of size $2^{32} \text{ bytes}$. Assume the computer system has a direct-mapped cache of size $32 KB (1 KB = 2^{10} \text{ bytes})$, and each cache block is of size 64 bytes.
The size of the tag field is __________ bits.
 A 22 B 15 C 17 D 19
GATE CSE 2021 SET-1   Computer Organization
Question 6 Explanation:
 Question 7
How many total bits are required for a direct-mapped cache with 128 KB of data and 1 word block size, assuming a 32-bit address and 1 word size of 4 bytes?
 A 2 Mbits B 1.7 Mbits C 2.5 Mbits D 1.5 Mbits
ISRO CSE 2020   Computer Organization
Question 7 Explanation:
 Question 8
Which of the following is an efficient method of cache updating?
 A Snoopy writes B Write through C Write within D Buffered write
ISRO CSE 2020   Computer Organization
Question 8 Explanation:
 Question 9
A computer system with a word length of 32 bits has a 16 MB byte- addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.

A1=0x42C8A4,
A2=0x546888,
A3=0x6A289C,
A4=0x5E4880

Which one of the following is TRUE?
 A A1 and A4 are mapped to different cache sets. B A2 and A3 are mapped to the same cache set. C A3 and A4 are mapped to the same cache set. D A1 and A3 are mapped to the same cache set.
GATE CSE 2020   Computer Organization
Question 9 Explanation:
 Question 10
A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is______.
 A 8.2 B 6.25 C 13.5 D 15.2
GATE CSE 2020   Computer Organization
Question 10 Explanation:
There are 10 questions to complete.

### 2 thoughts on “Cache Memory”

1. Question 2 answer must be 0.85 .. 0.84 was incorrect in the answer key