Cache Memory

Question 1
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

S1: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2
S2: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct?
A
S1 is true and S2 is false
B
S1 is false and S2 is true
C
S1 is true and S2 is true
D
S1 is false and S2 is false
GATE CSE 2021 SET-2   Computer Organization
Question 2
Consider a set-associative cache of size 2KB (1KB=2^{10} bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32 -bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is ______
A
2
B
4
C
8
D
16
GATE CSE 2021 SET-2   Computer Organization
Question 3
Consider a computer system with a byte-addressable primary memory of size 2^{32} \text{ bytes}. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB = 2^{10} \text{ bytes}), and each cache block is of size 64 bytes.
The size of the tag field is __________ bits.
A
22
B
15
C
17
D
19
GATE CSE 2021 SET-1   Computer Organization
Question 4
How many total bits are required for a direct-mapped cache with 128 KB of data and 1 word block size, assuming a 32-bit address and 1 word size of 4 bytes?
A
2 Mbits
B
1.7 Mbits
C
2.5 Mbits
D
1.5 Mbits
ISRO CSE 2020   Computer Organization
Question 5
Which of the following is an efficient method of cache updating?
A
Snoopy writes
B
Write through
C
Write within
D
Buffered write
ISRO CSE 2020   Computer Organization
Question 6
A computer system with a word length of 32 bits has a 16 MB byte- addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.

A1=0x42C8A4,
A2=0x546888,
A3=0x6A289C,
A4=0x5E4880

Which one of the following is TRUE?
A
A1 and A4 are mapped to different cache sets.
B
A2 and A3 are mapped to the same cache set.
C
A3 and A4 are mapped to the same cache set.
D
A1 and A3 are mapped to the same cache set.
GATE CSE 2020   Computer Organization
Question 7
A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is______.
A
8.2
B
6.25
C
13.5
D
15.2
GATE CSE 2020   Computer Organization
Question 8
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache-miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is _________\times 10^6 bytes/sec.
A
80
B
160
C
320
D
128
GATE CSE 2019   Computer Organization
Question 9
A certain processor uses a fully associative cache of size 16 kB, The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?
A
24 bits and 0 bits
B
28 bits and 4 bits
C
24 bits and 4 bits
D
28 bits and 0 bits
GATE CSE 2019   Computer Organization
Question 10
For a multi-processor architecture, in which protocol a write transaction is forwarded to only those processors that are known to possess a copy of newly altered cache line?
A
Snoopy bus protocol
B
Cache coherency protocol
C
Directory based protocol
D
None of the above
ISRO CSE 2018   Computer Organization
There are 10 questions to complete.

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