# Combinational Circuit

 Question 1
Which one of the following circuits implements the Boolean function given below?

$f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$

where $m_i$ is the $i^{th}$ minterm.

 A A B B C C D D
GATE CSE 2021 SET-2   Digital Logic
Question 1 Explanation:
 Question 2
Consider the following circuit

The function by the network above is
 A $\overline{A B} E+E F+\overline{C D} F$ B $(\bar{E}+A B \bar{F})(C+D+\bar{F})$ C $(\overline{A B}+E)(\bar{E}+\bar{F})(C+D+\bar{F})$ D $(A+B) \bar{E}+\overline{E F}+C D \bar{F}$
ISRO CSE 2020   Digital Logic
Question 2 Explanation:
 Question 3
Following Multiplexer circuit is equivalent to

 A Sum equation of full adder B Carry equation of full adder C Borrow equation for full subtractor D Difference equation of a full subtractor
ISRO CSE 2020   Digital Logic
Question 3 Explanation:
 Question 4
In a 8-bit ripple carry adder using identical full adders, each full adder takes 34 ns for computing sum. If the time taken for 8-bit addition is 90 ns, find time taken by each full adder to find carry.
 A 6 ns B 7 ns C 10 ns D 8 ns
ISRO CSE 2020   Digital Logic
Question 4 Explanation:
 Question 5
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m+n is ________ .
 A 20 B 2048 C 1034 D 1024
GATE CSE 2020   Digital Logic
Question 5 Explanation:
 Question 6
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is ______.
 A 8 B 32 C 5 D 6
GATE CSE 2020   Digital Logic
Question 6 Explanation:
 Question 7
When two 8-bit numbers $A_{7}....A_{0}$ and $B_{7}....B_{0}$ in 2's complement representation (with $A_{0}$ and $B_{0}$ as the least significant bits ) are added using a ripple-carry Combinational Circuit, the sum bits obtained are $S_{7}....S_{0}$ and the carry bits are $C_{7}....C_{0}$. An overflow is said to have occurred if
 A the carry bit $C_{7}$ is 1 B all the carry bits ($C_{7}....C_{0}$) are 1 C $(A_{7}B_{7}\bar{S_{7}}+\bar{A_{7}}\bar{B_{7}}S_{7})$ is 1 D $(A_{0}B_{0}\bar{S_{0}}+\bar{A_{0}}\bar{B_{0}}S_{0})$ is 1
GATE CSE 2017 SET-1   Digital Logic
Question 7 Explanation:
 Question 8
The circuit given in the figure below is

 A An oscillating circuit and its output is square wave B The one whose output remains stable in '1' state C The one having output remains stable in '0' state D has a single pulse of three times propagation delay
ISRO CSE 2016   Digital Logic
Question 8 Explanation:
 Question 9
The logic circuit given below converts a binary code y1, y2, y3 into

 A Excess-3 code B Gray code C BCD code D Hamming code
ISRO CSE 2016   Digital Logic
Question 9 Explanation:
 Question 10
For a binary half-subtractor having two inputs A and B, the correct set of logical outputs D(=A minus B) and X(=borrow) are
 A $D=AB+\bar{A}B, X=\bar{A}B$ B $D=\bar{A}B+A\bar{B}, X=A\bar{B}$ C $D=\bar{A}B+A\bar{B}, X=\bar{A} B$ D $D=AB+\bar{A}B, X=A\bar{B}$
ISRO CSE 2016   Digital Logic
Question 10 Explanation:
There are 10 questions to complete.

### 4 thoughts on “Combinational Circuit”

1. Question number 37, correct answer is option A. Please update it.