Computer Organization

Question 1
A processor X_1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X_2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X_1 and X_2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X_2 over X_1 in executing P is
A
0.72
B
1.42
C
0.64
D
1.64
GATE CSE 2022      Pipeline Processor
Question 2
Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?
MSQ
A
Every access to S is a hit.
B
Once P is brought to the cache it is never evicted.
C
At the end of the execution only R and S reside in the cache.
D
Every access to R evicts Q from the cache.
GATE CSE 2022      Cache Memory
Question 3
Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?

A
P is 10:1 multiplexer;
Q is 5:1 multiplexer;
T is 2:1 multiplexer
B
P is 10:2^{10} decoder;
Q is 5:2^{5} decoder;
T is 2:1 encoder
C
P is 10:2^{10} decoder;
Q is 5:2^{5} decoder;
T is 2:1 multiplexer
D
P is 1:10 de-multiplexer;
Q is 1:5 de-multiplexer;
T is 2:1 multiplexer
GATE CSE 2022      ALU Data Path and Control Unit
Question 4
A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access latency to 15 ns, whereas the miss penalty is not affected. The minimum hit rate (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is _____.
A
0.92
B
0.88
C
0.76
D
0.85
GATE CSE 2022      Cache Memory
Question 5
Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?
MSQ
A
Each cache block in WB and WT has a dirty bit.
B
Every write hit in WB leads to a data transfer from cache to main memory.
C
Eviction of a block from WT will not lead to data transfer from cache to main memory.
D
A read miss in WB will never lead to eviction of a dirty block from WB.
GATE CSE 2022      Cache Memory
Question 6
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?
A
DMA based I/O transfer
B
Interrupt driven I/O transfer
C
Polling based I/O transfer
D
Programmed I/O transfer
GATE CSE 2022      IO Interface
Question 7
Consider a pipelined processor with 5 stages, Instruction Fetch(IF), Instruction Decode(ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and the register read is performed in the EX stage, The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies.
Consider the following sequence of 8 instructions:

ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL

Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The speedup defined as follows.

\textit{Speedup} = \dfrac{\text{Execution time without operand forwarding}}{\text{Execution time with operand forearding}}

The Speedup achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is _____________
A
2.58
B
6.37
C
1.45
D
1.87
GATE CSE 2021 SET-2      Pipeline Processor
Question 8
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

S1: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2
S2: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct?
A
S1 is true and S2 is false
B
S1 is false and S2 is true
C
S1 is true and S2 is true
D
S1 is false and S2 is false
GATE CSE 2021 SET-2      Cache Memory
Question 9
Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is __________ bits per second.
A
10000
B
80000
C
40000
D
20000
GATE CSE 2021 SET-2      IO Interface
Question 10
Consider a set-associative cache of size 2KB (1KB=2^{10} bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32 -bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is ______
A
2
B
4
C
8
D
16
GATE CSE 2021 SET-2      Cache Memory


There are 10 questions to complete.

2 thoughts on “Computer Organization”

  1. Just one thing i want to share is that “whenever i want to go and solve questions from 10-36 pages .. i have to go downwards and click on the page number u have listed .. i can’t directly jump over the 25 or 32 page no. please make this web pages slightly less time consuming . cos everytime i have to open atleast 10 pages before seeing the 20 pages . Kindly make it more user friendly .

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