Computer Organization


Question 1
An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET.
The number of bits in the TAG is ____.
A
18
B
19
C
20
D
21
GATE CSE 2023      Cache Memory
Question 2
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11-IA0 are connected to the address port of these blocks. The chip select (CS) is active high.

The input memory addresses (IA11-IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?
A
(0, 1, 2, 3)
B
(0, 1024, 2048, 3072)
C
(0, 8, 16, 24)
D
(0, 0, 0, 0)
GATE CSE 2023      Memory Chip Design


Question 3
Consider the given C-code and its corresponding assembly code, with a few operands U1-U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.

Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?
A
(8, 4, 1, Lo2)
B
(3, 4, 4, Lo1)
C
(8, 1, 1, Lo2)
D
(3, 1, 1, Lo1)
GATE CSE 2023      Machine Instruction
Question 4
A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 \mu s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 \mu s to process the keystroke. Let T_1 denote the fraction of a second spent in polling and processing a keystroke.
In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let T_2 denote the fraction of a second spent in servicing the interrupt and processing a keystroke. The ratio \frac{T_1}{T_2} is ______ . (Rounded off to one decimal place)
A
2.5
B
15.3
C
8.5
D
10.2
GATE CSE 2023      Interrupt
Question 5
Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.
The total execution time for executing 100 instructions on this processor is _______ ns
A
2541
B
2040
C
1825
D
2358
GATE CSE 2023      Pipeline Processor




There are 5 questions to complete.

3 thoughts on “Computer Organization”

  1. Just one thing i want to share is that “whenever i want to go and solve questions from 10-36 pages .. i have to go downwards and click on the page number u have listed .. i can’t directly jump over the 25 or 32 page no. please make this web pages slightly less time consuming . cos everytime i have to open atleast 10 pages before seeing the 20 pages . Kindly make it more user friendly .

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  2. please make the page size dynamic like home many questions we want to see on the page. I usually love to see 10-15 questions per page. If this is made dynamic then user can see based on their requirements.

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