# Computer Organization

 Question 1
Consider a pipelined processor with 5 stages, Instruction Fetch(IF), Instruction Decode(ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and the register read is performed in the EX stage, The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies.
Consider the following sequence of 8 instructions:

Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The speedup defined as follows.

$\textit{Speedup} = \dfrac{\text{Execution time without operand forwarding}}{\text{Execution time with operand forearding}}$

The Speedup achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is _____________
 A 2.58 B 6.37 C 1.45 D 1.87
GATE CSE 2021 SET-2      Pipeline Processor
Question 1 Explanation:
 Question 2
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

S1: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2
S2: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct?
 A S1 is true and S2 is false B S1 is false and S2 is true C S1 is true and S2 is true D S1 is false and S2 is false
GATE CSE 2021 SET-2      Cache Memory
Question 2 Explanation:
 Question 3
Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is __________ bits per second.
 A 10000 B 80000 C 40000 D 20000
GATE CSE 2021 SET-2      IO Interface
Question 3 Explanation:
 Question 4
Consider a set-associative cache of size 2KB ($1KB=2^{10}$ bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32 -bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is ______
 A 2 B 4 C 8 D 16
GATE CSE 2021 SET-2      Cache Memory
Question 4 Explanation:
 Question 5
Consider the following instruction sequence where registers $R_1,R_2 \text{ and }R_3$ are general purpose and $MEMORY[X]$ denotes the content at the memory location $X$.

$\begin{array}{llc} \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size} \text{ (bytes)} \\ \hline \text{MOV } R1, (5000) & R1 \leftarrow \text{MEMORY}[5000] & 4 \\ \hline \text{MOV } R2, (R3) & R2 \leftarrow \text{MEMORY}[R3] & 4 \\ \hline \text{ADD} R2, R1 & R2 \leftarrow R1 + R2 & 2 \\ \hline \text{MOV } (R3), R2 & \text{MEMORY}[R3] \leftarrow R2 & 4 \\ \hline \text{INC } R3 & R3 \leftarrow R3+1 & 2 \\ \hline \text{DEC } R1 & R1 \leftarrow R1-1 & 2 \\ \hline \text{BNZ } 1004 & \text{Branch if not zero to the} & 2 \\ & \text{given absolute address} \\ \hline \text{HALT} & \text{Stop} & 1 \\ \hline \end{array}$

Assume that the content of the memory location 5000 is 10, and the content of the register $R_3$ is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable.
After the execution of the program, the content of memory location 3010 is ____________
 A 50 B 100 C 60 D 110
GATE CSE 2021 SET-1      Machine Instruction
Question 5 Explanation:
 Question 6
A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.
The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
 A 17080 B 16335 C 17160 D 16640
GATE CSE 2021 SET-1      Pipeline Processor
Question 6 Explanation:
 Question 7
Consider a computer system with a byte-addressable primary memory of size $2^{32} \text{ bytes}$. Assume the computer system has a direct-mapped cache of size $32 KB (1 KB = 2^{10} \text{ bytes})$, and each cache block is of size 64 bytes.
The size of the tag field is __________ bits.
 A 22 B 15 C 17 D 19
GATE CSE 2021 SET-1      Cache Memory
Question 7 Explanation:
 Question 8
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called
 A True dependency B Anti-dependency C Output dependency D Control Hazard
ISRO CSE 2020      Pipeline Processor
Question 8 Explanation:
 Question 9
How many total bits are required for a direct-mapped cache with 128 KB of data and 1 word block size, assuming a 32-bit address and 1 word size of 4 bytes?
 A 2 Mbits B 1.7 Mbits C 2.5 Mbits D 1.5 Mbits
ISRO CSE 2020      Cache Memory
Question 9 Explanation:
 Question 10
A magnetic disk has 100 cylinders, each with 10 tracks of 10 sectors. If each sector contains 128 bytes, what is the maximum capacity of the disk in kilobytes?
 A 12,80,000 B 1280 C 1250 D 1,28,000
ISRO CSE 2020      Secondary Storage
Question 10 Explanation:

There are 10 questions to complete.