Question 1 |
A certain processor uses a fully associative cache of size 16 kB, The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?
24 bits and 0 bits | |
28 bits and 4 bits | |
24 bits and 4 bits | |
28 bits and 0 bits |
Question 1 Explanation:
Question 2 |
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A_{15} \; to \; A_0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?


C800 to CFFF | |
CA00 to CAFF | |
C800 to C8FF | |
DA00 to DFFF |
Question 2 Explanation:
Question 3 |
Which one of the following kinds of derivation is used by LR parsers?
Leftmost | |
Leftmost in reverse | |
Rightmost | |
Rightmost in reverse |
Question 3 Explanation:
Question 4 |
In 16-bit 2's complement representation, the decimal number -28 is:
1111 1111 0001 1100 | |
0000 0000 1110 0100 | |
1111 1111 1110 0100 | |
1000 0000 1110 0100 |
Question 4 Explanation:
Question 5 |
Let U=\{1,2,,...n\}. Let A=\{(x,X)|x\in X,X\subseteq U\}. Consider the following two statements on |A|.
I. |A|=n2^{n-1}
II. |A|=\sum_{k=1}^{n}k\binom{n}{k}
Which of the above statements is/are TRUE?
I. |A|=n2^{n-1}
II. |A|=\sum_{k=1}^{n}k\binom{n}{k}
Which of the above statements is/are TRUE?
Only I | |
Only II | |
Both I and II | |
Neither I nor II |
Question 5 Explanation:
There are 5 questions to complete.