# GATE CSE 2019

 Question 1
A certain processor uses a fully associative cache of size 16 kB, The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?
 A 24 bits and 0 bits B 28 bits and 4 bits C 24 bits and 4 bits D 28 bits and 0 bits
Computer Organization   Cache Memory
Question 1 Explanation:
 Question 2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by $A_{15} \; to \; A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
 A C800 to CFFF B CA00 to CAFF C C800 to C8FF D DA00 to DFFF
Computer Organization   Memory Chip Design
Question 2 Explanation:

 Question 3
Which one of the following kinds of derivation is used by LR parsers?
 A Leftmost B Leftmost in reverse C Rightmost D Rightmost in reverse
Compiler Design   Parsing
Question 3 Explanation:
 Question 4
In 16-bit 2's complement representation, the decimal number -28 is:
 A 1111 1111 0001 1100 B 0000 0000 1110 0100 C 1111 1111 1110 0100 D 1000 0000 1110 0100
Digital Logic   Number System
Question 4 Explanation:
 Question 5
Let $U=\{1,2,,...n\}$. Let $A=\{(x,X)|x\in X,X\subseteq U\}$. Consider the following two statements on |A|.

I. $|A|=n2^{n-1}$
II. $|A|=\sum_{k=1}^{n}k\binom{n}{k}$

Which of the above statements is/are TRUE?
 A Only I B Only II C Both I and II D Neither I nor II
Discrete Mathematics   Set Theory
Question 5 Explanation:

There are 5 questions to complete.