GATE IT 2007

Question 1
Suppose there are two coins. The first coin gives heads with probability \dfrac{5}{8} when tossed, while the second coin gives heads with probability \dfrac{1}{4}. One of the two coins is picked up at random with equal probability and tossed. What is the probability of obtaining heads ?
A
\left(\dfrac{7}{8}\right)
B
\left(\dfrac{1}{2}\right)
C
\left(\dfrac{7}{16}\right)
D
\left(\dfrac{5}{32}\right)
Discrete Mathematics   Probability Theory
Question 2
Let A be the matrix \begin{bmatrix}3 &1 \\ 1&2\end{bmatrix}. What is the maximum value of x^TAx where the maximum is taken over all x that are the unit eigenvectors of A?
A
5
B
\frac{(5 + \sqrt{5})}{2}
C
3
D
\frac{(5 - \sqrt{5})}{2}
Engineering Mathematics   Linear Algebra
Question 3
Consider a weighted, undirected graph with positive edge weights and let uv be an edge in the graph. It is known that the shortest path from the source vertex s to u has weight 53 and the shortest path from s to v has weight 65. Which one of the following statements is always TRUE?
A
Weight (u,v) \leq 12
B
Weight (u,v) = 12
C
Weight (u,v) \geq 12
D
Weight (u,v) > 12
Algorithm   Shortest Path
Question 4
In the Spiral model of software development, the primary determinant in selecting activities in each iteration is
A
Iteration size
B
Cost
C
Adopted process such as Rational Unified Process or Extreme Programming
D
Risk
Software Engg   
Question 5
Which of the following systems is a most likely candidate example of a pipe and filter architecture ?
A
Expert system
B
DB repository
C
Aircraft flight controller
D
Signal processing
Software Engg   
Question 6
A processor takes 12 cycles to complete an instruction I. The corresponding pipelined processor uses 6 stages with the execution times of 3, 2, 5, 4, 6 and 2 cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed?
A
1.83
B
2
C
3
D
6
Computer Organization   Pipeline Processor
Question 7
Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?
A
11, 00
B
01, 10
C
10, 01
D
00, 11
Digital Logic   Sequential Circuit
Question 8
The following circuit implements a two-input AND gate using two 2-1 multiplexers.

What are the values of X_1, X_2, X_3?
A
X_1 = b, X_2 = 0, X_3 = a
B
X_1 = b, X_2 = 1, X_3 = b
C
X_1 = a, X_2 = b, X_3 = 1
D
X_1 = a, X_2 = 0, X_3 = b
Digital Logic   Combinational Circuit
Question 9
Consider an ambiguous grammar G and its disambiguated version D. Let the language recognized by the two grammars be denoted by L(G) and L(D) respectively. Which one of the following is true?
A
L (D) \subset L (G)
B
L (D) \supset L (G)
C
L (D) = L (G)
D
L (D) is empty
Compiler Design   Parsing
Question 10
Processes P1 and P2 use critical_flag in the following routine to achieve mutual exclusion. Assume that critical_flag is initialized to FALSE in the main program.
 get_exclusive_access ( )
{
    if (critical _flag == FALSE) {
        critical_flag = TRUE ;
        critical_region () ;
        critical_flag = FALSE;
    }
}

Consider the following statements.

i.It is possible for both P1 and P2 to access critical_region concurrently.
ii.This may lead to a deadlock.

Which of the following holds?
A
(i) is false (ii) is true
B
Both (i) and (ii) are false
C
(i) is true (ii) is false
D
Both (i) and (ii) are true
Operating System   Process Synchronization
There are 10 questions to complete.

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