Interrupt

Question 1
Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts.
II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.
III. In polling,the CPU periodically checks the status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?
A
I and II only
B
I and IV only
C
I and III only
D
III only
GATE CSE 2020   Computer Organization
Question 2
The following are some events that occur after a device controller issues an interrupt while process L is under execution.
(P) The processor pushes the process status of L onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of L from the control stack.
(T) The processor loads the new PC value based on the interrupt.
Which one of the following is the correct order in which the events above occur?
A
QPTRS
B
PTRSQ
C
TRPQS
D
QTPRS
GATE CSE 2018   Computer Organization
Question 3
Which interrupt in 8085 Microprocessor is unmaskable?
A
RST 5.5
B
RST 7.5
C
TRAP
D
Both (A) and (B)
ISRO CSE 2017   Computer Organization
Question 4
In 8085 microprocessor, the ISR for handling trap interrupt is at which location?
A
3CH
B
34H
C
74H
D
24H
ISRO CSE 2013   Computer Organization
Question 5
A computer handles several interrupt sources of which the following are relevant for this question.

Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high)
Interrupt from Mouse (raises Interrupt if the mouse is moved or a button is pressed)
Interrupt from Keyboard (raises Interrupt if a key is pressed or released)
Interrupt from Hard Disk (raises Interrupt when a disk read is completed)

Which one of these will be handled at the HIGHEST priority?
A
Interrupt from Hard Disk
B
Interrupt from Mouse
C
Interrupt from Keyboard
D
Interrupt from CPU temp sensor
GATE CSE 2011   Computer Organization
Question 6
On receiving an interrupt from an I/O device,the CPU
A
Halts for a predetermined time
B
Branches off to the interrupt service routine after completion of the current instruction
C
Branches off to the interrupt service routine immediately
D
Hands over control of address bus and data bus to the interrupting device
ISRO CSE 2009   Computer Organization
Question 7
A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interruptsI_1, I_2 and I_3 require the following execution time after the interrupt is recognized:
I. I_1 requires 25 microseconds
II. I_2 requires 35 microseconds
III. I_3 requires 20 microseconds
I_1 has the highest priority and I_3 has the lowest. What is the possible range of time for I_3 to be executed assuming that it may or may not occur simultaneously with other interrupts?
A
24.5 microseconds to 39.5 microseconds
B
24.5 microseconds to 93.5 microseconds
C
4.5 microseconds to 24.5 microseconds
D
29.5 microseconds 93.5 microseconds
ISRO CSE 2009   Computer Organization
Question 8
Which of the following statements about synchronous and asynchronous I/O is NOT true?
A
An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O
B
In both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is invoked after completion of the I/O
C
A process making a synchronous I/O call waits until I/O is complete, but a process making an asynchronous I/O call does not wait for completion of the I/O
D
In the case of synchronous I/O, the process waiting for the completion of I/O is woken up by the ISR that is invoked after the completion of I/O
ISRO CSE 2009   Computer Organization
Question 9
A CPU generally handles an interrupt by executing an interrupt service routine
A
As soon as an interrupt is raised
B
By checking the interrupt register at the end of fetch cycle.
C
By checking the interrupt register after finishing the execution of the current instruction.
D
By checking the interrupt register at fixed time intervals.
GATE CSE 2009   Computer Organization
Question 10
The TRAP is one of the interrupts available in INTEL 8085. Which one of the following statements is true of TRAP ?
A
it is level triggered
B
it is negative edge triggered
C
it is +ve edge triggered
D
it is both +ve and -ve edges triggered
ISRO CSE 2008   Computer Organization
There are 10 questions to complete.

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