# Interrupt

 Question 1
A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 $\mu s$ (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 $\mu s$ to process the keystroke. Let $T_1$ denote the fraction of a second spent in polling and processing a keystroke.
In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let $T_2$ denote the fraction of a second spent in servicing the interrupt and processing a keystroke. The ratio $\frac{T_1}{T_2}$ is ______ . (Rounded off to one decimal place)
 A 2.5 B 15.3 C 8.5 D 10.2
GATE CSE 2023   Computer Organization
Question 1 Explanation:
 Question 2
Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts.
II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.
III. In polling,the CPU periodically checks the status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?
 A I and II only B I and IV only C I and III only D III only
GATE CSE 2020   Computer Organization
Question 2 Explanation:

 Question 3
The following are some events that occur after a device controller issues an interrupt while process L is under execution.
(P) The processor pushes the process status of L onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of L from the control stack.
(T) The processor loads the new PC value based on the interrupt.
Which one of the following is the correct order in which the events above occur?
 A QPTRS B PTRSQ C TRPQS D QTPRS
GATE CSE 2018   Computer Organization
Question 3 Explanation:
 Question 4
Which interrupt in 8085 Microprocessor is unmaskable?
 A RST 5.5 B RST 7.5 C TRAP D Both (A) and (B)
ISRO CSE 2017   Computer Organization
Question 4 Explanation:
 Question 5
In 8085 microprocessor, the ISR for handling trap interrupt is at which location?
 A 3CH B 34H C 74H D 24H
ISRO CSE 2013   Computer Organization
Question 5 Explanation:

There are 5 questions to complete.

### 2 thoughts on “Interrupt”

1. Sir Question no. 5 is incomplete….