Question 1 |
Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is __________ bits per second.
10000 | |
80000 | |
40000 | |
20000 |
Question 1 Explanation:
Question 2 |
Of the following, which best characterizes computers that use memory-mapped I/O?
The computer provides special instructions for manipulating I/O ports | |
I/O ports are placed at addresses on the bus and are accessed just like other memory locations | |
To perform I/O operations. it is sufficient to place the data in an address register and call channel to perform the operation | |
I/O can be performed only when memory management hardware is turned on |
Question 2 Explanation:
Question 3 |
The size of the data count register of a DMA controller is 16 bits.The processor needs to transfer a file of 29,154 kilobytes from disk to main memory.The memory is byte addressable. The minimum number of times the DMA control lerneeds to get the control of the systembus from the processor to transfer the file from the disk to main memory is ____.
1 | |
456 | |
228 | |
114 |
Question 3 Explanation:
Question 4 |
A processor is fetching instructions at the rate of 1 MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at 9600 bps. How much time will the processor be slowed down due to DMA activity?
9.6ms | |
4.8ms | |
2.4ms | |
1.2ms |
Question 4 Explanation:
Question 5 |
In DMA transfer scheme, the transfer scheme other than burst mode is
cycle technique | |
stealing technique | |
cycle stealing technique | |
cycle bypass technique |
Question 5 Explanation:
Question 6 |
On a non-pipelined sequential processor, a program segment, which is a part of
the interrupt service routine, is given to transfer 500 bytes from an I/O device to
memory.
Initialize the address register
Initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.
The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
Initialize the address register
Initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.
The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
3.4 | |
4.4 | |
5.1 | |
6.7 |
Question 6 Explanation:
Question 7 |
Which of the following is an example of spooled device?
A line printer used to print the output of a number of jobs | |
A terminal used to enter input data to a running program | |
A secondary storage device in a virtual memory system | |
A graphic display device |
Question 7 Explanation:
Question 8 |
The device which is used to connect a peripheral to bus is known as
control register | |
interface | |
communication protocol | |
none of these |
Question 8 Explanation:
Question 9 |
The ability to temporarily halt the CPU and use this time to send information on buses is called
direct memory access | |
vectoring the interrupt | |
polling | |
cycle stealing |
Question 9 Explanation:
Question 10 |
Which of the following statements about synchronous and asynchronous I/O is
NOT true?
An ISR is invoked on completion of I/O in synchronous I/O but not in
asynchronous I/O | |
In both synchronous and asynchronous I/O, an ISR (Interrupt Service
Routine) is invoked after completion of the I/O | |
A process making a synchronous I/O call waits until I/O is complete, but a process making an asynchronous I/O call does not wait for completion of the I/O | |
In the case of synchronous I/O, the process waiting for the completion of I/O
is woken up by the ISR that is invoked after the completion of I/O |
Question 10 Explanation:
There are 10 questions to complete.
In question number 14, please update the interrupt overhead from 4secs to 4microsecs.
Thank You Mounika Dasa,
We have updated the question.
Please update the answer of Q20, on GateOverflow the correct answer is given as option A.
Thank You Sudeep Chowdhary,
We have updated the answer.