# ISRO CSE 2020

 Question 1
The immediate addressing mode can be used for
2. Perform arithmetic or logical operation on data contained in instructions
Which of the following is true?
 A Only 1 B Only 2 C Both 1 and 2 D Immediate mode refers to data in cache
Question 1 Explanation:
 Question 2
Statements associated with registers of a CPU are given. Identify the false statement.
 A The program counter holds the memory address of the instruction in execution B Only opcode is transferred to the control unit C An instruction in the instruction register consists of the opcode and the operand D The value of the program counter is incremented by 1 once its value has been read to the memory address register
Computer Organization   Machine Instruction
Question 2 Explanation:
 Question 3
Which of the following affects the processing power assuming they do not influence each other
1. Data bus capability
3. Clock speed
 A 3 only B 1 and 3 only C 2 and 3 only D 1,2 and 3
Computer Organization
Question 3 Explanation:
 Question 4
Convert the pre-fix expression to in-fix $-^{*}+A B C^{*}-D E+F G$
 A $(A-B)^{*} C+\left(D^{*} E\right)-(F+G)$ B $(A+B)^{*} C-(D-E)^{*}(F-G)$ C $(A+B-C)^{*}(D-E)^{*}(F+G)$ D $(((A+B)*C)-((D-E)*(F+G)))$
Data Structure   Stack
Question 4 Explanation:
Originally all Options are wrong. We have modified one option.
 Question 5
An array of 2 two byte integers is stored in big endian machine in byte addresses as shown below. What will be its storage pattern in little endian machine ?
$\begin{array}{c|c}\text{Address}& \text{Data}\\\hline0 \times 104&78\\0 \times 103&56\\0 \times 102&34\\0 \times 101&12\end{array}$
 A $\begin{array}{c|c}\text{Address}& \text{Data}\\\hline0 \times 104&12\\0 \times 103&56\\0 \times 102&34\\0 \times 101&78\end{array}$ B $\begin{array}{c|c}\text{Address}& \text{Data}\\\hline0 \times 104&12\\0 \times 103&34\\0 \times 102&56\\0 \times 101&78\end{array} \\$ C $\begin{array}{c|c}\text{Address}& \text{Data}\\\hline0 \times 104&56\\0 \times 103&78\\0 \times 102&12\\0 \times 101&34\end{array} \\$ D $\begin{array}{c|c}\text{Address}& \text{Data}\\\hline0 \times 104&56\\0 \times 103&12\\0 \times 102&78\\0 \times 101&34\end{array}$
Question 5 Explanation:
 Question 6
A non-pipelined CPU has 12 general purpose registers?(R0,R1,R2,...,R12). Following operations are supported

ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr
MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr

MUL operation takes two clock cycles, ADD takes one clock cycle.

Calculate minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variable X,Y,Z are initially available in registers R0,R1 and R2 and contents of these registers must not be modified.
 A 5 B 6 C 7 D 8
Computer Organization   Machine Instruction
Question 6 Explanation:
 Question 7
Consider a 5- segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline)
 A 5 B 4.03 C 4.81 D 4.17
Computer Organization   Pipeline Processor
Question 7 Explanation:
 Question 8
Consider a 32- bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?
 A 32 B 64 C 128 D 16
Computer Organization   Machine Instruction
Question 8 Explanation:
 Question 9
In a 8-bit ripple carry adder using identical full adders, each full adder takes 34 ns for computing sum. If the time taken for 8-bit addition is 90 ns, find time taken by each full adder to find carry.
 A 6 ns B 7 ns C 10 ns D 8 ns
Digital Logic   Combinational Circuit
Question 9 Explanation:
 Question 10
Following Multiplexer circuit is equivalent to

 A Sum equation of full adder B Carry equation of full adder C Borrow equation for full subtractor D Difference equation of a full subtractor
Digital Logic   Combinational Circuit
Question 10 Explanation:
There are 10 questions to complete.