Machine Instruction

Question 1
Consider the following instruction sequence where registers R_1,R_2 \text{ and }R_3 are general purpose and MEMORY[X] denotes the content at the memory location X.

\begin{array}{llc} \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size} \text{ (bytes)} \\ \hline \text{MOV } R1, (5000) & R1 \leftarrow \text{MEMORY}[5000] & 4 \\ \hline \text{MOV } R2, (R3) & R2 \leftarrow \text{MEMORY}[R3] & 4 \\ \hline \text{ADD} R2, R1 & R2 \leftarrow R1 + R2 & 2 \\ \hline \text{MOV } (R3), R2 & \text{MEMORY}[R3] \leftarrow R2 & 4 \\ \hline \text{INC } R3 & R3 \leftarrow R3+1 & 2 \\ \hline \text{DEC } R1 & R1 \leftarrow R1-1 & 2 \\ \hline \text{BNZ } 1004 & \text{Branch if not zero to the} & 2 \\ & \text{given absolute address} \\ \hline \text{HALT} & \text{Stop} & 1 \\ \hline \end{array}

Assume that the content of the memory location 5000 is 10, and the content of the register R_3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable.
After the execution of the program, the content of memory location 3010 is ____________
A
50
B
100
C
60
D
110
GATE CSE 2021 SET-1   Computer Organization
Question 2
A computer which issues instructions in order, has only 2 registers and 3 opcodes ADD, SUB and MOV. Consider 2 different implementations of the following basic block :
\begin{array}{l|l} \text { Case } 1 & \text { Case } 2 \\ \hline t 1=a+b ; & t 2=c+d \\ t 2=c+d ; & t 3=e-t 2 \\ t 3=e-t 2 ; & t 1=a+b \\ t 4=t 1-t 2 ; & t 4=t 1-t 2 \end{array}
Assume that all operands are initially in memory. Final value of computation also has to reside in memory. Which one is better in terms of memory accesses and by how many MOV instructions?
A
Case 2, 2
B
Case 2, 3
C
Case 1, 2
D
Case 1, 3
ISRO CSE 2020   Computer Organization
Question 3
Consider a 32- bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?
A
32
B
64
C
128
D
16
ISRO CSE 2020   Computer Organization
Question 4
A non-pipelined CPU has 12 general purpose registers?(R0,R1,R2,...,R12). Following operations are supported

ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr
MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr

MUL operation takes two clock cycles, ADD takes one clock cycle.

Calculate minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variable X,Y,Z are initially available in registers R0,R1 and R2 and contents of these registers must not be modified.
A
5
B
6
C
7
D
8
ISRO CSE 2020   Computer Organization
Question 5
Statements associated with registers of a CPU are given. Identify the false statement.
A
The program counter holds the memory address of the instruction in execution
B
Only opcode is transferred to the control unit
C
An instruction in the instruction register consists of the opcode and the operand
D
The value of the program counter is incremented by 1 once its value has been read to the memory address register
ISRO CSE 2020   Computer Organization
Question 6
A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.
A
16
B
8
C
14
D
12
GATE CSE 2020   Computer Organization
Question 7
Consider the following data path diagram.

Consider an instruction: R0\leftarrow R1+R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

1. \; R2_r,TEMP1_r,ALU_{add},TEMP2_w
2. \; R1_r,TEMP1_w
3. \; PC_r,MAR_w,MEM_r
4. \; TEMP2_r,R0_w
5. \; MDR_r,IR_w

Which one of the following is the correct order of execution of the above steps?
A
2,1,4,5,3
B
1,2,4,3,5
C
3,5,2,1,4
D
3,5,1,2,4
GATE CSE 2020   Computer Organization
Question 8
A byte addressable computer has a memory capacity of 2^{m} K B(k \text { bytes }) and can perform 2^{n} operations. An instruction involving 3 operands and one operator needs maximum of:
A
3m bits
B
3m+n bits
C
m+n bits
D
none of the above
ISRO CSE 2018   Computer Organization
Question 9
A data driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code:

A. Multiply E by 0.5 to get F
B. Add A and B to get E
C. Add B with 0.5 to get D
D. Add E and F to get G
E. Add A with 10.5 to get C

Assume A,B,C are already assigned values and the desired output is G. Which of the following sequence of execution is valid?
A
B, C, D, A, E
B
C, B, E, A, D
C
A, B, C, D, E
D
E, D, C, B, A
ISRO CSE 2018   Computer Organization
Question 10
A processor has 16 integer registers (R0, R1,...,R15) and 64 floating point registers (F0, F1,...,F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).
The maximum value of N is __________.
A
8
B
16
C
32
D
64
GATE CSE 2018   Computer Organization
There are 10 questions to complete.

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