Question 1 |

Consider the given C-code and its corresponding assembly code, with a few
operands U1-U4 being unknown. Some useful information as well as the semantics
of each unique assembly instruction is annotated as inline comments in the code.
The memory is byte-addressable.

Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?

Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?

(8, 4, 1, Lo2) | |

(3, 4, 4, Lo1) | |

(8, 1, 1, Lo2) | |

(3, 1, 1, Lo1) |

Question 1 Explanation:

Question 2 |

Consider the following instruction sequence where registers R_1,R_2 \text{ and }R_3 are general purpose and MEMORY[X] denotes the content at the memory location X.

\begin{array}{llc} \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size} \text{ (bytes)} \\ \hline \text{MOV } R1, (5000) & R1 \leftarrow \text{MEMORY}[5000] & 4 \\ \hline \text{MOV } R2, (R3) & R2 \leftarrow \text{MEMORY}[R3] & 4 \\ \hline \text{ADD} R2, R1 & R2 \leftarrow R1 + R2 & 2 \\ \hline \text{MOV } (R3), R2 & \text{MEMORY}[R3] \leftarrow R2 & 4 \\ \hline \text{INC } R3 & R3 \leftarrow R3+1 & 2 \\ \hline \text{DEC } R1 & R1 \leftarrow R1-1 & 2 \\ \hline \text{BNZ } 1004 & \text{Branch if not zero to the} & 2 \\ & \text{given absolute address} \\ \hline \text{HALT} & \text{Stop} & 1 \\ \hline \end{array}

Assume that the content of the memory location 5000 is 10, and the content of the register R_3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable.

After the execution of the program, the content of memory location 3010 is ____________

\begin{array}{llc} \textbf{Instruction} & \textbf{Semantics} & \textbf{Instruction Size} \text{ (bytes)} \\ \hline \text{MOV } R1, (5000) & R1 \leftarrow \text{MEMORY}[5000] & 4 \\ \hline \text{MOV } R2, (R3) & R2 \leftarrow \text{MEMORY}[R3] & 4 \\ \hline \text{ADD} R2, R1 & R2 \leftarrow R1 + R2 & 2 \\ \hline \text{MOV } (R3), R2 & \text{MEMORY}[R3] \leftarrow R2 & 4 \\ \hline \text{INC } R3 & R3 \leftarrow R3+1 & 2 \\ \hline \text{DEC } R1 & R1 \leftarrow R1-1 & 2 \\ \hline \text{BNZ } 1004 & \text{Branch if not zero to the} & 2 \\ & \text{given absolute address} \\ \hline \text{HALT} & \text{Stop} & 1 \\ \hline \end{array}

Assume that the content of the memory location 5000 is 10, and the content of the register R_3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable.

After the execution of the program, the content of memory location 3010 is ____________

50 | |

100 | |

60 | |

110 |

Question 2 Explanation:

Question 3 |

A computer which issues instructions in order, has only 2 registers and 3 opcodes ADD, SUB and MOV. Consider 2 different implementations of the following basic block :

\begin{array}{l|l} \text { Case } 1 & \text { Case } 2 \\ \hline t 1=a+b ; & t 2=c+d \\ t 2=c+d ; & t 3=e-t 2 \\ t 3=e-t 2 ; & t 1=a+b \\ t 4=t 1-t 2 ; & t 4=t 1-t 2 \end{array}

Assume that all operands are initially in memory. Final value of computation also has to reside in memory. Which one is better in terms of memory accesses and by how many MOV instructions?

\begin{array}{l|l} \text { Case } 1 & \text { Case } 2 \\ \hline t 1=a+b ; & t 2=c+d \\ t 2=c+d ; & t 3=e-t 2 \\ t 3=e-t 2 ; & t 1=a+b \\ t 4=t 1-t 2 ; & t 4=t 1-t 2 \end{array}

Assume that all operands are initially in memory. Final value of computation also has to reside in memory. Which one is better in terms of memory accesses and by how many MOV instructions?

Case 2, 2 | |

Case 2, 3 | |

Case 1, 2 | |

Case 1, 3 |

Question 3 Explanation:

Question 4 |

Consider a 32- bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?

32 | |

64 | |

128 | |

16 |

Question 4 Explanation:

Question 5 |

A non-pipelined CPU has 12 general purpose registers?(R0,R1,R2,...,R12). Following operations are supported

ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr

MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr

MUL operation takes two clock cycles, ADD takes one clock cycle.

Calculate minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variable X,Y,Z are initially available in registers R0,R1 and R2 and contents of these registers must not be modified.

ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr

MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr

MUL operation takes two clock cycles, ADD takes one clock cycle.

Calculate minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variable X,Y,Z are initially available in registers R0,R1 and R2 and contents of these registers must not be modified.

5 | |

6 | |

7 | |

8 |

Question 5 Explanation:

There are 5 questions to complete.

Please update in question number 55 the correct answer is option B.

Thank You Aditya,

We have updated the answer.