Memory Chip Design

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A_{15} \; to \; A_0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M x 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^{14}. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.

How many 128x8 bit RAMs are required to design 32Kx32 bit RAM?

How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?

Suppose you want to build a memory with 4 byte words and a capacity of 2^{21} bits. What is type of decoder required if the memory is built using 2K \times 8 RAM chips?

If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 \times 6 array, where each chip is 8K \times 4 bits ?

A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4 decoders with enable line needed to construct a 16K x 16 RAM from 1K x 8 RAM is

The amount of ROM needed to implement a 4 bit multiplier is

Number of chips (128 \times 8 RAM) needed to provide a memory capacity of 2048 bytes

A main memory unit with a capacity of 4 megabytes is built using 1Mx1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is