Memory Chip Design

Question 1
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A_{15} \; to \; A_0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
A
C800 to CFFF
B
CA00 to CAFF
C
C800 to C8FF
D
DA00 to DFFF
GATE CSE 2019   Computer Organization
Question 2
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M x 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^{14}. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.
A
60
B
65
C
55
D
70
GATE CSE 2018   Computer Organization
Question 3
How many 128x8 bit RAMs are required to design 32Kx32 bit RAM?
A
512
B
1024
C
128
D
32
ISRO CSE 2017   Computer Organization
Question 4
How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
A
8
B
32
C
64
D
128
ISRO CSE 2015   Computer Organization
Question 5
Suppose you want to build a memory with 4 byte words and a capacity of 2^{21} bits. What is type of decoder required if the memory is built using 2K \times 8 RAM chips?
A
5 to 32
B
6 to 64
C
4 to 16
D
7 to 128
ISRO CSE 2014   Computer Organization
Question 6
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 \times 6 array, where each chip is 8K \times 4 bits ?
A
13
B
15
C
16
D
17
ISRO CSE 2014   Computer Organization
Question 7
A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4 decoders with enable line needed to construct a 16K x 16 RAM from 1K x 8 RAM is
A
4
B
5
C
6
D
7
GATE CSE 2013   Computer Organization
Question 8
The amount of ROM needed to implement a 4 bit multiplier is
A
64 bits
B
128 bits
C
1 Kbits
D
2 Kbits
GATE CSE 2012   Computer Organization
Question 9
Number of chips (128 \times 8 RAM) needed to provide a memory capacity of 2048 bytes
A
2
B
4
C
8
D
16
ISRO CSE 2011   Computer Organization
Question 10
A main memory unit with a capacity of 4 megabytes is built using 1Mx1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
A
100 nanoseconds
B
100 *2^{10} nanoseconds
C
100*2^{20} nanoseconds
D
3200*2^{20} nanoseconds
GATE CSE 2010   Computer Organization
There are 10 questions to complete.

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