Memory Chip Design


Question 1
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11-IA0 are connected to the address port of these blocks. The chip select (CS) is active high.

The input memory addresses (IA11-IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?
A
(0, 1, 2, 3)
B
(0, 1024, 2048, 3072)
C
(0, 8, 16, 24)
D
(0, 0, 0, 0)
GATE CSE 2023   Computer Organization
Question 2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A_{15} \; to \; A_0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
A
C800 to CFFF
B
CA00 to CAFF
C
C800 to C8FF
D
DA00 to DFFF
GATE CSE 2019   Computer Organization


Question 3
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M x 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^{14}. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.
A
60
B
65
C
55
D
70
GATE CSE 2018   Computer Organization
Question 4
How many 128x8 bit RAMs are required to design 32Kx32 bit RAM?
A
512
B
1024
C
128
D
32
ISRO CSE 2017   Computer Organization
Question 5
How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
A
8
B
32
C
64
D
128
ISRO CSE 2015   Computer Organization


There are 5 questions to complete.

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