Question 1 |
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A_{15} \; to \; A_0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?


C800 to CFFF | |
CA00 to CAFF | |
C800 to C8FF | |
DA00 to DFFF |
Question 1 Explanation:
Question 2 |
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M x 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^{14}. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.
60 | |
65 | |
55 | |
70 |
Question 2 Explanation:
Question 3 |
How many 128x8 bit RAMs are required to design 32Kx32 bit RAM?
512 | |
1024 | |
128 | |
32 |
Question 3 Explanation:
Question 4 |
How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
8 | |
32 | |
64 | |
128 |
Question 4 Explanation:
Question 5 |
Suppose you want to build a memory with 4 byte words and a capacity of 2^{21} bits. What is type of decoder required if the memory is built using 2K \times 8 RAM chips?
5 to 32 | |
6 to 64 | |
4 to 16 | |
7 to 128 |
Question 5 Explanation:
Question 6 |
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 \times 6 array, where each chip is 8K \times 4 bits ?
13 | |
15 | |
16 | |
17 |
Question 6 Explanation:
Question 7 |
A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4 decoders
with enable line needed to construct a 16K x 16 RAM from 1K x 8 RAM is
4 | |
5 | |
6 | |
7 |
Question 7 Explanation:
Question 8 |
The amount of ROM needed to implement a 4 bit multiplier is
64 bits | |
128 bits | |
1 Kbits | |
2 Kbits |
Question 8 Explanation:
Question 9 |
Number of chips (128 \times 8 RAM) needed to provide a memory capacity of 2048 bytes
2 | |
4 | |
8 | |
16 |
Question 9 Explanation:
Question 10 |
A main memory unit with a capacity of 4 megabytes is built using 1Mx1-bit
DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The
time taken for a single refresh operation is 100 nanoseconds. The time required
to perform one refresh operation on all the cells in the memory unit is
100 nanoseconds | |
100 *2^{10} nanoseconds | |
100*2^{20} nanoseconds | |
3200*2^{20} nanoseconds |
Question 10 Explanation:
There are 10 questions to complete.
Sir Question 20
Correct option is B
Thank You Ankur Maurya,
We have updated the option.