Memory Management


Question 1
Consider a computer system with 57-bit virtual addressing using multi-level tree-structured page tables with L levels for virtual to physical address translation. The page size is 4 KB (1 KB = 1024 B) and a page table entry at any of the levels occupies 8 bytes.
The value of L is ______.
A
4
B
5
C
6
D
7
GATE CSE 2023   Operating System
Question 2
Consider the following two-dimensional array D in the C programming language, which is stored in row-major order:

int D[128][128];

Demand paging is used for allocating memory and each physical page frame holds 512 elements of the array D. The Least Recently Used (LRU) page-replacement policy is used by the operating system. A total of 30 physical page frames are allocated to a process which executes the following code snippet:

for (int i = 0; i < 128; i++)
       for (int j = 0; j < 128; j++) 
                   D[j][i] *= 10;

The number of page faults generated during the execution of this code snippet is _____.
A
128
B
4096
C
1024
D
2048
GATE CSE 2023   Operating System


Question 3
Consider a demand paging system with four page frames (initially empty) and LRU page replacement policy. For the following page reference string

7, 2, 7, 3, 2, 5, 3, 4, 6, 7, 7,1, 5, 6,1

the page fault rate, defined as the ratio of number of page faults to the number of memory accesses (rounded off to one decimal place) is
A
0.4
B
0.5
C
0.6
D
0.7
GATE CSE 2022   Operating System
Question 4
Which one of the following statements is FALSE?
A
The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address.
B
If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory.
C
The memory access time using a given inverted page table is always same for all incoming virtual addresses.
D
In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same.
GATE CSE 2022   Operating System
Question 5
Consider a three-level page table to translate a 39-bit virtual address to a physical address as shown below:

The page size is 4 KB = (1KB =2^{10} bytes) and page table entry size at every level is 8 bytes. A process P is currently using 2 GB (1 GB =2^{30} bytes) virtual memory which os mapped to 2 GB of physical memory. The minimum amount of memory required for the page table of P across all levels is _________ KB
A
1024
B
4096
C
4108
D
1864
GATE CSE 2021 SET-2   Operating System




There are 5 questions to complete.

6 thoughts on “Memory Management”

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