Sequential Circuit

Question 1
Consider a 3-bit counter, designed using T flip-flops, as shown below:

Assuming the initial state of the counter given by PQR as 000, what are the next three states?
A
011,101,000
B
001,010,111
C
011,101,111
D
001,010,000
GATE CSE 2021 SET-1   Digital Logic
Question 2
A new flipflop with inputs X and Y, has the following property
\begin{array}{|c|c|c|c|} \hline \mathbf{X} & \mathbf{Y} & \text { Current state } & \text { Next state } \\ \hline 0 & 0 & Q & 1 \\ 0 & 1 & Q & \bar{Q} \\ 1 & 1 & Q & 0 \\ 1 & 0 & Q & Q \\ \hline \end{array}
Which of the following expresses the next state in terms of X,Y, current state?
A
(\bar{X} \wedge \bar{Q}) \vee(\bar{Y} \wedge Q)
B
(\bar{X} \wedge {Q}) \vee(\bar{Y} \wedge \bar{Q})
C
({X} \wedge \bar{Q}) \vee({Y} \wedge {Q})
D
({X} \wedge \bar{Q}) \vee(\bar{Y} \wedge {Q})
ISRO CSE 2020   Digital Logic
Question 3
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is _____.
A
1
B
2
C
3
D
4
GATE CSE 2018   Digital Logic
Question 4
Advantage of synchronous sequential circuits over asynchronous one is :
A
Lower hardware requirement
B
Better noise immunity
C
Faster operation
D
All of the above
ISRO CSE 2017   Digital Logic
Question 5
The next state table of a 2-bit saturating up-counter is given below.
\begin{matrix} Q_{1} & Q_{0} & Q_{1}^{+} &Q_{0}^{+} \\ 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0\\ 1 & 0 & 1 & 1\\ 1 & 1 & 1 & 1 \end{matrix}
The counter is built as a synchronous sequential circuit using T flip-flops. The expression for T_1 \; and \; T_0 are
A
T_{1}=Q_{1} Q_{0} , \; \; T_{0}=\bar{Q_{1}}\bar{Q_{0}}
B
T_{1}=\bar{Q_{1}} Q_{0} , \; \; T_{0}=\bar{Q_{1}}+\bar{Q_{0}}
C
T_{1}=Q_{1} + Q_{0} , \; \; T_{0}=\bar{Q_{1}}+\bar{Q_{0}}
D
T_{1}=Q_{1} Q_{0} , \; \; T_{0}=\bar{Q_{1}}+\bar{Q_{0}}
GATE CSE 2017 SET-2   Digital Logic
Question 6
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop

Initailly, both Q_{0} and Q_{1} are set to 1 (before the 1st clock cycle). The outputs
A
Q_{1}Q_{0} after 3rd cycle are 11 and after the 4th cycle are 00 respectively
B
Q_{1}Q_{0} after 3rd cycle are 11 and after the 4th cycle are 01 respectively
C
Q_{1}Q_{0} after 3rd cycle are 00 and after the 4th cycle are 11 respectively
D
Q_{1}Q_{0} after 3rd cycle are 01 and after the 4th cycle are 01 respectively
GATE CSE 2017 SET-1   Digital Logic
Question 7
The functional difference between SR flip-flop and J-K flip-flop is that :
A
J -K flip-flop is faster than SR flip-flop
B
J-K flip-flop has a feedback path
C
J-K flip-flop accepts both inputs 1
D
None of them
ISRO CSE 2016   Digital Logic
Question 8
We want to design a synchronous counter that counts these quence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip flop srequired to implement this counteris ________.
A
3
B
4
C
5
D
2
GATE CSE 2016 SET-1   Digital Logic
Question 9
A modulus -12 ring counter requires a minimum of
A
10 flip-flops
B
12 flip-flops
C
8 flip-flops
D
6 flip-flops
ISRO CSE 2015   Digital Logic
Question 10
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,...) is __________ .
A
2
B
3
C
4
D
5
GATE CSE 2015 SET-2   Digital Logic
There are 10 questions to complete.

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