Question 1 |

Consider a 3-bit counter, designed using T flip-flops, as shown below:

Assuming the initial state of the counter given by PQR as 000, what are the next three states?

Assuming the initial state of the counter given by PQR as 000, what are the next three states?

011,101,000 | |

001,010,111 | |

011,101,111 | |

001,010,000 |

Question 1 Explanation:

Question 2 |

A new flipflop with inputs X and Y, has the following property

\begin{array}{|c|c|c|c|} \hline \mathbf{X} & \mathbf{Y} & \text { Current state } & \text { Next state } \\ \hline 0 & 0 & Q & 1 \\ 0 & 1 & Q & \bar{Q} \\ 1 & 1 & Q & 0 \\ 1 & 0 & Q & Q \\ \hline \end{array}

Which of the following expresses the next state in terms of X,Y, current state?

\begin{array}{|c|c|c|c|} \hline \mathbf{X} & \mathbf{Y} & \text { Current state } & \text { Next state } \\ \hline 0 & 0 & Q & 1 \\ 0 & 1 & Q & \bar{Q} \\ 1 & 1 & Q & 0 \\ 1 & 0 & Q & Q \\ \hline \end{array}

Which of the following expresses the next state in terms of X,Y, current state?

(\bar{X} \wedge \bar{Q}) \vee(\bar{Y} \wedge Q) | |

(\bar{X} \wedge {Q}) \vee(\bar{Y} \wedge \bar{Q}) | |

({X} \wedge \bar{Q}) \vee({Y} \wedge {Q}) | |

({X} \wedge \bar{Q}) \vee(\bar{Y} \wedge {Q}) |

Question 2 Explanation:

Question 3 |

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is _____.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is _____.

1 | |

2 | |

3 | |

4 |

Question 3 Explanation:

Question 4 |

Advantage of synchronous sequential circuits over asynchronous one is :

Lower hardware requirement | |

Better noise immunity | |

Faster operation | |

All of the above |

Question 4 Explanation:

Question 5 |

The next state table of a 2-bit saturating up-counter is given below.

\begin{matrix} Q_{1} & Q_{0} & Q_{1}^{+} &Q_{0}^{+} \\ 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0\\ 1 & 0 & 1 & 1\\ 1 & 1 & 1 & 1 \end{matrix}

The counter is built as a synchronous sequential circuit using T flip-flops. The expression for T_1 \; and \; T_0 are

\begin{matrix} Q_{1} & Q_{0} & Q_{1}^{+} &Q_{0}^{+} \\ 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0\\ 1 & 0 & 1 & 1\\ 1 & 1 & 1 & 1 \end{matrix}

The counter is built as a synchronous sequential circuit using T flip-flops. The expression for T_1 \; and \; T_0 are

T_{1}=Q_{1} Q_{0} , \; \; T_{0}=\bar{Q_{1}}\bar{Q_{0}} | |

T_{1}=\bar{Q_{1}} Q_{0} , \; \; T_{0}=\bar{Q_{1}}+\bar{Q_{0}} | |

T_{1}=Q_{1} + Q_{0} , \; \; T_{0}=\bar{Q_{1}}+\bar{Q_{0}} | |

T_{1}=Q_{1} Q_{0} , \; \; T_{0}=\bar{Q_{1}}+\bar{Q_{0}} |

Question 5 Explanation:

Question 6 |

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop

Initailly, both Q_{0} and Q_{1} are set to 1 (before the 1st clock cycle). The outputs

Initailly, both Q_{0} and Q_{1} are set to 1 (before the 1st clock cycle). The outputs

Q_{1}Q_{0} after 3rd cycle are 11 and after the 4th cycle are 00 respectively | |

Q_{1}Q_{0} after 3rd cycle are 11 and after the 4th cycle are 01 respectively | |

Q_{1}Q_{0} after 3rd cycle are 00 and after the 4th cycle are 11 respectively | |

Q_{1}Q_{0} after 3rd cycle are 01 and after the 4th cycle are 01 respectively |

Question 6 Explanation:

Question 7 |

The functional difference between SR flip-flop and J-K flip-flop is that :

J -K flip-flop is faster than SR flip-flop | |

J-K flip-flop has a feedback path | |

J-K flip-flop accepts both inputs 1 | |

None of them |

Question 7 Explanation:

Question 8 |

We want to design a synchronous counter that counts these quence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip flop srequired to implement this counteris ________.

3 | |

4 | |

5 | |

2 |

Question 8 Explanation:

Question 9 |

A modulus -12 ring counter requires a minimum of

10 flip-flops | |

12 flip-flops | |

8 flip-flops | |

6 flip-flops |

Question 9 Explanation:

Question 10 |

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,...) is __________ .

2 | |

3 | |

4 | |

5 |

Question 10 Explanation:

There are 10 questions to complete.

please correct Qestion number 8

Answer is 4 Not 3

Thank You PRAFUL devendra,

We have updated the answer.

Update the first question the options are not correct its scrambled

Thank You Neeraj Hebbar,

We have updated the option

Q27 options are wrong..

a option should be 0110