Question 1 |
Consider the circuit shown with an ideal OPAMP. The output voltage V_o is
__________V (rounded off to two decimal places).
0.5 | |
0.75 | |
-0.5 | |
-0.75 |
Question 1 Explanation:
V_A=\frac{V_R}{2} \; and R_{th}=R
V_B=\frac{V_B}{2}
V_C=\frac{(V_R+V_R/4)}{2}=\frac{5}{8}V_R
R_{th}=2R||2R=R
Similarly,
V_D=\frac{V_C}{2}=\frac{5}{16}V_R
So, \frac{S}{16}V_R=\frac{5}{16} \times 1.6V
V_o=\frac{-3R}{(2R+R)} \times \frac{5}{16} \times 1.6=-\frac{3}{2} \times \frac{5}{16} \times 1.6
V_o=-0.5V
Question 2 |
An 8-bit unipolar (all analog output values are positive) digital-to-analog converter (DAC) has a full-scale voltage range from 0\; V
to 7.68\:V. If the digital input code is 10010110
(the leftmost bit is \text{MSB}), then the analog output voltage of the DAC (rounded off to one decimal place) is ___________ V.
2.4 | |
4.5 | |
8.4 | |
5.4 |
Question 2 Explanation:
\begin{aligned} \text { Given: } \qquad \qquad V_{p s}&=7.68 \mathrm{~V} \\ n &=8 \mathrm{bit} \\ \text { Resolution }(k) &=\frac{V_{F S}}{2^{n}-1}=\frac{7.68}{2^{8}-1}=0.03\\ \text { Now, } \quad V_{\mathrm{DAC}}&=k \times\{\text { Decimal equivalent }\}\\ &=0.03 \times\{150\} \\ &=4.5 \mathrm{~V} \end{aligned}
Question 3 |
A 10-bit D/A converter is calibrated over the full range from 0 to 10 V. If the input to
the D/A converter is 13A (in hex), the output (rounded off to three decimal places) is
_________ V.
3.069 | |
1.214 | |
2.124 | |
0.257 |
Question 3 Explanation:
Given, n=10
V_{FS}=10\, V
Input Voltage=(13A)_{16}=(314)_{10}
Output Voltage=Resolution X Decimal Equivalent of input
V_{o}=\frac{10}{2^{10}-1}\times 314=3.069\, V
V_{FS}=10\, V
Input Voltage=(13A)_{16}=(314)_{10}
Output Voltage=Resolution X Decimal Equivalent of input
V_{o}=\frac{10}{2^{10}-1}\times 314=3.069\, V
Question 4 |
In an N bit flash ADC, the analog voltage is fed simultaneously to 2^{N}-1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source V_{in} (whose output is being converted to digital format) has a source resistance of 75 \Omega as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF.
The input must settle to an accuracy of 1/2 LSB even for a full scale input change for proper conversion. Assume that the time taken by the thermometer to binary encoder is negligible.
If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate ?
If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate ?
1 megasamples per second | |
6 megasamples per second | |
64 megasamples per second | |
256 megasamples per second |
Question 5 |
Consider a four bit D to A converter. The analog value corresponding to digital signals of values 0000 and 0001 are 0 V and 0.0625 V respectively. The analog value (in Volts) corresponding to the digital signal 1111 is ________.
0.7 | |
0.93 | |
1.13 | |
1.07 |
Question 5 Explanation:
Step size =0.0625 \mathrm{V}
Decimal equivalent =15
Analog output =15 \times 0.0625=0.9375 Volts
Decimal equivalent =15
Analog output =15 \times 0.0625=0.9375 Volts
Question 6 |
The output of a 3-stage Johnson (twisted ring) counter is fed to a digital-to
analog (D/A) converter as shown in the figure below. Assume all the states
of the counter to be unset initially. The waveform which represents the D/A
converter output v_{o} is
A | |
B | |
C | |
D |
Question 6 Explanation:
Sequence of Johnson counter is
\begin{array}{ccccccc} Q_{2} & Q_{1} & Q_{0} & D_{2} & D_{1} & D_{0} & V_{0} \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 1 & 0 & 0 & 4 \\ 1 & 1 & 0 & 1 & 1 & 0 & 6 \\ 1 & 1 & 1 & 1 & 1 & 1 & 7 \\ 0 & 1 & 1 & 0 & 1 & 1 & 3 \\ 0 & 0 & 1 & 0 & 0 & 1 & 1 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 \end{array}
\begin{array}{ccccccc} Q_{2} & Q_{1} & Q_{0} & D_{2} & D_{1} & D_{0} & V_{0} \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 1 & 0 & 0 & 4 \\ 1 & 1 & 0 & 1 & 1 & 0 & 6 \\ 1 & 1 & 1 & 1 & 1 & 1 & 7 \\ 0 & 1 & 1 & 0 & 1 & 1 & 3 \\ 0 & 0 & 1 & 0 & 0 & 1 & 1 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 \end{array}
Question 7 |
In the following circuit, the comparator output is logic "1" if V_{1} \gt V_{2} and is logic "0" otherwise. The D/A conversion is done as per the relations
V_{DAC}=\sum_{n=0}^{3}2^{n-1}b_{n} Volts, where b_{3} (MSB), b_{2}, b_{1}, b_{0}(LSB) are the counter outputs.
The counter starts from the clear state.
The magnitude of the error between V_{DAC} and V_{in} at steady state in volts is
V_{DAC}=\sum_{n=0}^{3}2^{n-1}b_{n} Volts, where b_{3} (MSB), b_{2}, b_{1}, b_{0}(LSB) are the counter outputs.
The counter starts from the clear state.
The magnitude of the error between V_{DAC} and V_{in} at steady state in volts is
0.2 | |
0.3 | |
0.5 | |
1 |
Question 7 Explanation:
Magnitude of the error between V_{\mathrm{DAC}} and V_{\text {in }} at steady state
=6.5-6.2=0.3 \mathrm{V}
=6.5-6.2=0.3 \mathrm{V}
Question 8 |
In the following circuit, the comparator output is logic "1" if V_{1} \gt V_{2} and is logic "0" otherwise. The D/A conversion is done as per the relations
V_{DAC}=\sum_{n=0}^{3}2^{n-1}b_{n} Volts, where b_{3} (MSB), b_{2}, b_{1}, b_{0}(LSB) are the counter outputs.
The counter starts from the clear state.
The stable reading of the LED displays is
V_{DAC}=\sum_{n=0}^{3}2^{n-1}b_{n} Volts, where b_{3} (MSB), b_{2}, b_{1}, b_{0}(LSB) are the counter outputs.
The counter starts from the clear state.
The stable reading of the LED displays is
6 | |
7 | |
12 | |
13 |
Question 8 Explanation:
\begin{aligned} V_{\mathrm{DAC}} &=2^{-1} b_{0}+2^{\circ} b_{1}+2^{1} b_{2}+2^{2} b_{3} \\ &=0.5 b_{0}+b_{1}+2 b_{2}+4 b_{3} \end{aligned}
Counter output will start from 0000 and will increase by 1 at every clock pulse.
Table for V_{\mathrm{DAC}} is shown below
\begin{array}{cccc|c} b_{3} & b_{2} & b_{1} & b_{0} & V_{\text {DAC }} \\ \hline 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0.5 \\ 0 & 0 & 1 & 0 & 1 \\ 0 & 0 & 1 & 1 & 1.5 \\ 0 & 1 & 0 & 0 & 2 \\ 0 & 1 & 0 & 1 & 2.5 \\ 0 & 1 & 1 & 0 & 3 \\ 0 & 1 & 1 & 1 & 3.5 \\ 1 & 0 & 0 & 0 & 4 \\ 1 & 0 & 0 & 1 & 4.5 \\ 1 & 0 & 1 & 0 & 5 \\ 1 & 0 & 1 & 1 & 5.5 \\ 1 & 1 & 0 & 0 & 6 \\ 1 & 1 & 0 & 1 & 6.5 \\ 1 & 1 & 1 & 0 & 7 \\ 1 & 1 & 1 & 1 & 7.5 \end{array}
Counter will increase till V_{\text {in }} \gt V_{\text {DAC. }}. So, when V_{\text {DAC }} =6.5V, the comparator output will be zero and the counter will be stable at that reading. The corresponding reading of LED display is 13.
Counter output will start from 0000 and will increase by 1 at every clock pulse.
Table for V_{\mathrm{DAC}} is shown below
\begin{array}{cccc|c} b_{3} & b_{2} & b_{1} & b_{0} & V_{\text {DAC }} \\ \hline 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0.5 \\ 0 & 0 & 1 & 0 & 1 \\ 0 & 0 & 1 & 1 & 1.5 \\ 0 & 1 & 0 & 0 & 2 \\ 0 & 1 & 0 & 1 & 2.5 \\ 0 & 1 & 1 & 0 & 3 \\ 0 & 1 & 1 & 1 & 3.5 \\ 1 & 0 & 0 & 0 & 4 \\ 1 & 0 & 0 & 1 & 4.5 \\ 1 & 0 & 1 & 0 & 5 \\ 1 & 0 & 1 & 1 & 5.5 \\ 1 & 1 & 0 & 0 & 6 \\ 1 & 1 & 0 & 1 & 6.5 \\ 1 & 1 & 1 & 0 & 7 \\ 1 & 1 & 1 & 1 & 7.5 \end{array}
Counter will increase till V_{\text {in }} \gt V_{\text {DAC. }}. So, when V_{\text {DAC }} =6.5V, the comparator output will be zero and the counter will be stable at that reading. The corresponding reading of LED display is 13.
Question 9 |
In the Digital-to-Analog converter circuit shown in the figure below, V_{R}=10 V and R = 10K\Omega
The voltage V_{o} is
The voltage V_{o} is
-0.781 V | |
-1.562 V | |
-3.125 V | |
-6.250 V |
Question 9 Explanation:
Net current in inverting terminal of op-amp
\begin{aligned} &=\frac{I}{4}+\frac{I}{16}=\frac{5 I}{16} \\ V_{0} &=-R \times \frac{5 I}{16} \\ =&-\frac{10 \times 10^{3} \times 5 \times 1 \times 10^{-3}}{16}=-3.125 \mathrm{V} \end{aligned}
\begin{aligned} &=\frac{I}{4}+\frac{I}{16}=\frac{5 I}{16} \\ V_{0} &=-R \times \frac{5 I}{16} \\ =&-\frac{10 \times 10^{3} \times 5 \times 1 \times 10^{-3}}{16}=-3.125 \mathrm{V} \end{aligned}
Question 10 |
In the Digital-to-Analog converter circuit shown in the figure below, V_{R}=10 V and R = 10K\Omega
The current i is
The current i is
31.25 \muA | |
62.5 \muA | |
125 \muA | |
250\muA |
Question 10 Explanation:
Last both 2R resister are in parallel and series with R then after
then again similar condition last both 2R are in parallel and series with R similarly after solving equivalent circuit is
I=\frac{V_{R}}{R}=\frac{10}{10 \mathrm{k} \Omega}=1 \mathrm{mA}
then i=\frac{I}{16}=\frac{1 \times 10^{-3}}{16}=62.5 \mu \mathrm{A}
There are 10 questions to complete.