# Analog Circuits

 Question 1
In the voltage regulator shown below, $V_l$ is the unregulated at 15 V. Assume $V_{BE}$= 0.7 V and the base current is negligible for both the BJTs. If the regulated output $V_O$ is 9 V, the value of $R_2$ is ________ $\Omega$.
 A 1000 B 800 C 400 D 200
GATE EC 2020      BJT Analysis
Question 1 Explanation:
\begin{aligned}9\times \frac{R_{2}}{R_{2}+1K\Omega }&=4 \\ 9R_{2}&=4R_{2}+4K\Omega\\ 5R_{2}&=4K \\ R_{2}&=\frac{4000}{5}=800\Omega \end{aligned}
 Question 2
The components in the circuit given below are ideal. If R = 2 $k\Omega$ and C = 1 $\mu F$, the -3 dB cut-off frequency of the circuit in Hz is
 A 14.92 B 34.46 C 59.68 D 79.58
GATE EC 2020      Operational Amplifiers
Question 2 Explanation:
Op-amp active filter (LPF) inverting type 3 dB cut-off frequency,
$f_{c}=\frac{1}{2\pi RC}=\frac{1}{2\pi \times 2\times 10^{3}\times 10^{-6}}=\frac{500}{2\pi }=79.58Hz$
 Question 3
Using the incremental low frequency small-signal model of the MOS device, the Norton equivalent resistance of the following circuit is
 A $r_{ds}+R+g_mr_{ds}R$ B $\frac{r_{ds} +R}{1+g_m r_{ds}}$ C $r_{ds}+\frac{1}{g_m}+R$ D $r_{ds}+R$
GATE EC 2020      FET and MOSFET Analysis
Question 3 Explanation:
\begin{aligned}v_{\pi }&=-V_{x} \\ V_{x}&=\left ( I_{x}-g_{m}V_{x} \right )r_{ds}+I_{x}R\\ V_{x}\left ( 1+g_{m} r_{ds}\right )&=\left ( r_{ds}+R \right )I_{x} \\ R_{N}&=\frac{V_{x}}{I_{x}}=\frac{R+r_{ds}}{1+g_{m}r_{ds}}\end{aligned}

 Question 4
An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to -10 V. If the input voltage $V_I$ lies between $\pm 10$ V, the minimum and the maximum values of $V_G$ required for proper sampling and holding respectively, are
 A 3V and -3 V B 10 V and -10 V C 13 V and -7 V D 10 V and -13 V
GATE EC 2020      FET and MOSFET Analysis
Question 4 Explanation:

for holding MOSFET should be OFF.
\begin{aligned}V_{1\, min}&\rightarrow -10\, V \\ V_{G}-V_{1\, min}& \lt 3 \\ V_{G}& \lt 3-10V\Rightarrow -7V \\ \text{For Sampling, } V_{G}-V_{i\, max}& \gt 3\\ V_{G}& \gt 3+V_{i\, max}\\ V_{G}&\gt 13\end{aligned}
 Question 5
For the BJT in the amplifier shown below, $V_{BE} = 0.7 V, kT/q = 26 mV$. Assume the BJT output resistance ($r_o$) is very high and the base current is negligible. The capacitors are also assumed to be short circuited at signal frequencies. The input $v_i$ is direct coupled. The low frequency gain $v_o/v_i$ of the amplifier is
 A -89.42 B -128.21 C -178.85 D -256.42
GATE EC 2020      BJT Analysis
Question 5 Explanation:
\begin{aligned}I_{EQ}&=\frac{10-0.7}{20}=0.465mA\\ g_{m}&=\frac{I_{EQ}}{V_{T}}=\frac{0.465}{26}A/V \\ \frac{V_{out}}{V_{in}}&=-g_{m}(R_{e}\parallel R_{L})\\ &=\frac{0.465}{26}\times 5000=-89.423\end{aligned}
 Question 6
In the circuit shown below, all the components are ideal. If $V_i$ is +2 V, the current $I_o$ sourced by the op-amp is __________ mA.
 A 4 B 6 C 2 D 1
GATE EC 2020      Operational Amplifiers
Question 6 Explanation:
\begin{aligned} V_o=(1+1) \times 2&=4V \\ \text{KCL at node } V_o & \\ \frac{2-4}{1k\Omega }I_o+\frac{0-4}{1k\Omega }&=0 \\ -2+I_o-4 &=0 \\ I_o&=6mA \end{aligned}
 Question 7
In the circuit shown below, all the components are ideal and the input voltage is sinusoidal. The magnitude of the steady-state output $V_0$ (rounded off to two decimal places) is _________ V.
 A 325.2 B 650.4 C 125.45 D 752.36
GATE EC 2020      Diodes Applications
Question 7 Explanation:
Voltage Doubles, $V_{o}=2\: V_{m}=2\times 230\sqrt{2}\cong 650.4V$
 Question 8
The components in the circuit shown below are ideal. If the op-amp is in positive feedback and the input voltage $V_i$ is a sine wave of amplitude 1 V, the output voltage $V_o$ is
 A a non-inverted sine wave of 2 V amplitude B an inverted sine wave of 1 V amplitude C a square wave of 5 V amplitude D a constant of either +5 or -5V
GATE EC 2020      Operational Amplifiers
Question 8 Explanation:

Given circuit is a Schmitt trigger of non-inverting type.
$V_{o}=\pm 5\, V$
$V^{+}=\frac{V_{o}\times 1+V_{i}\times 1}{1+1}=\frac{V_{o}+V}{2}$
let,$V_{o}=-5\, V,\, \, \, \,V^{+}=\frac{-5+V_{i}}{2}$
$V_{o}$ can change from -5 V to +5 V if $V^{+} \gt 0$
i.e. $\frac{-5+V_{i}}{2} \gt 0\Rightarrow V_{i} \gt 5\, V$
similarly, $V_{o}$ can change from -5 V to +5 V if $V_{i} \lt -5\, V$
But given input has peak value 1 V. Hence output cannot change from +5 V to -5 V or -5 V to +5 V.
Output remain constant at +5 V or -5 V.
 Question 9
In the circuit shown, $V_1=0 \; and \; V_2=V_{dd}$. The other relevant parameters are mentioned in the figure. Ignoring the effect of channel length modulation and the body effect, the value of $I_{out}$ is _____mA(rounded off to 1 decimal place).
 A 4.2 B 6 C 8.3 D 2.4
GATE EC 2019      FET and MOSFET Analysis
Question 9 Explanation:

\begin{aligned} \frac{I_{2}}{I_{1}} &=\frac{(W / L)_{2}}{(W / L)_{1}}=\frac{3}{2} \\ I_{2} &=\frac{3}{2} \times I_{1}=1.5 \mathrm{mA} \end{aligned}
$M_{3}$ is OFF because $V_{1}=0 \Rightarrow I_{3}=0$
$M_{4}$ is ON because $V_{2}=V_{D D}$
\begin{aligned} I_{5} &=I_{4}=I_{2}=1.5 \mathrm{mA} \\ \frac{I_{6}}{I_{5}} &=\frac{(W / L)_{6}}{(W / L)_{5}}=\frac{40}{10}=4 \\ I_{6} &=4 I_{5}=4 \times 1.5=6 \mathrm{mA} \\ \therefore \quad I_{\text {out }} &=I_{6}=6 \mathrm{mA} \end{aligned}
 Question 10
In the circuit shown, the threshold voltages of the pMOS (|$V_{tp}$|) and nMOS ($V_{tn}$) transistors are both equal to 1 V. All the transistors have the same output resistance $r_{ds}$ of 6 M$\Omega$. The other parameters are listed below:

$\mu_n C_{ox}=60\mu A/V^2$; $\left ( \frac{W}{L} \right )_{nMOS}=5$
$\mu_p C_{ox}=30\mu A/V^2$; $\left ( \frac{W}{L} \right )_{pMOS}=10$

$\mu_n \; and \; \mu_p$ are the carrier mobilities, and $C_{ox}$ is the oxide capacitance per unit area. Ignoring the effect of channel length modulation and body bias, the gain of the circuit is____ (rounded off to 1 decimal place).
 A -800 B -750.6 C -900 D -652.3
GATE EC 2019      FET and MOSFET Analysis
Question 10 Explanation:
$M_{3}$ and $M_{4}$ are identical PMOS transistor and they have equal current.
Hence their $V_{SG}$ should be equal.

\begin{aligned} V_{S G 3} &=V_{S G 4}=\frac{V_{D D}}{2}=2 V \\ I_{S D} &=\frac{\mu_{p} C_{o x}}{2}\left(\frac{W}{L}\right)_{p}\left(V_{S G}-\left|V_{T}\right|\right)^{2} \\ &=\frac{30}{2} \times 10(2-1)^{2}=150 \mu \mathrm{A} \end{aligned}
now, by using current mirror property all transistor should have equal current.
\begin{aligned} I_{\mathrm{DSN}}&=I_{\mathrm{SDP}}=150 \mu \mathrm{A} \\ \text { For } M_{1} \quad g_{m 1}&=\sqrt{2 \mu_{n} C_{o x} \frac{W}{L} \times I_{D S}} \\ &=\sqrt{2 \mu_{n} C_{0 x}} \frac{W}{L} \times I_{D S}\\ & =\sqrt{2 \times 60 \times 5 \times 150}=300 \mathrm{m} \end{aligned}
$M_{2}, M_{3}$ and $M_{4}$ from active load for $M_{1}$. This active load in equivalent to resistance $r_{d s 2} i.e. 6 \mathrm{M} \Omega$

$M_{1}$ is common source amplifier.
\begin{aligned} \therefore \quad \frac{V_{\text {out }}}{V_{\text {in }}} &=A_{v}=-g_{m 1} \times\left(r_{\text {ds2 }} \| r_{\text {ds1 }}\right) \\ &=-300 \mathrm{M} \mathrm{C} \times 3 \mathrm{M} \Omega=-900 \end{aligned}

There are 10 questions to complete.