Analog Circuits


Question 1
In the circuit below, the voltage V_{L} is ____ \_V.
(rounded off to two decimal places)

A
2
B
1.55
C
3.32
D
6.32
GATE EC 2023      FET and MOSFET Analysis
Question 1 Explanation: 


We know,
\begin{aligned} I_{D} & \propto\left(\frac{W}{L}\right) \\ I_{1} & =1 \mathrm{~mA} \\ I_{2} & =\frac{10}{1} \times 1=10 \mathrm{~mA} \\ I_{3} & =10 \mathrm{~mA} \\ I_{4} & =7 \mathrm{~mA} \\ I_{5} & =5 \mathrm{~mA} \\ I_{0} & =I_{4}-I_{5}=7-5=2 \mathrm{~mA} \\ V_{L} & =2 \times 1=2 \mathrm{~V} \end{aligned}
Question 2
In the circuit shown below, D_{1} and D_{2} are silicon diodes with cut-in voltage of 0.7 \mathrm{~V}. V_{\text {IN }} and V_{\text {OUT }} are input and output voltages in volts. The transfer characteristic is

A
A
B
B
C
C
D
D
GATE EC 2023      Diodes Applications
Question 2 Explanation: 
Case I:
\begin{aligned} V_{\gamma}&=0.7 \mathrm{~V} \\ \text { For the +ve half cycle } &\text { if input } V_{\text {in }} \\ D_{1} & \rightarrow O \mathrm{ON} \text { and } D_{2} \rightarrow \text { OFF } \\ \text { For diode } D_{1}:& \quad V_{\text {in }}-1 V \gt 0.7 \\ V_{\text {in }} & \gt 1.7 \mathrm{~V} \\ V_{0}&=V_{\text {in }}-0.7 \end{aligned}

Case II:
For the + ve half cycle if input V_{\text {in }},
D_{1} \rightarrow \mathrm{OFF} and D_{2} \rightarrow \mathrm{ON}

For diode D_{2}: \quad 1-V_{\text {in }} \gt 0.7
V_{\text {in }} \lt 0.3 \mathrm{~V}
V_{0}=V_{\text {in }}+0.7

Case III:
\begin{aligned} 0.3 \mathrm{~V} & \lt V_{\text {in }} \lt 1.7 \mathrm{~V} \\ D_{1} & \rightarrow \mathrm{OFF} \text { and } D_{2} \rightarrow \mathrm{OFF} \\ V_{0} & =1 \mathrm{~V} \end{aligned}
Transfer characteristics,



Question 3
The \frac{V_{\text {OUT }}}{V_{\text {IN }}} of the circuit shown below is

A
-\frac{R_{4}}{R_{3}}
B
\frac{R_{4}}{R_{3}}
C
1+\frac{R_{4}}{R_{3}}
D
1-\frac{R_{4}}{R_{3}}
GATE EC 2023      Operational Amplifiers
Question 3 Explanation: 


Here, A_{1} is an inverting amplifier and A_{2} is a non-inverting amplifier.
\begin{aligned} V_{01}&=\frac{-R_{2}}{R_{1}} V_{i n} \\ V_{02}&=\left(1+\frac{R_{2}}{R_{1}}\right) V_{i n} \end{aligned}

Also, A_{3} is an inverting summing amplifier,
\begin{aligned} V_{\text {out }} & =\frac{-R_{4}}{R_{3}} V_{01}-\frac{R_{4}}{R_{3}} V_{02}=\frac{-R_{4}}{R_{3}}\left[\frac{R_{2}}{R_{1}} V_{\text {in }}+\left(1+\frac{R_{2}}{R_{1}}\right) V_{\text {in }}\right] \\ V_{\text {out }} & =\frac{-R_{4}}{R_{3}} V_{\text {in }} \\ \text { Gain, } \frac{V_{\text {out }}}{V_{\text {in }}} & =\frac{-R_{4}}{R_{3}} \end{aligned}
Question 4
In the circuit shown below, V_{1} and V_{2} are bias voltages. Based on input and output impedances, the circuit behaves as a

A
voltage controlled voltage source.
B
voltage controlled current source.
C
current controlled voltage source.
D
current controlled current source.
GATE EC 2023      Feedback Amplifiers
Question 4 Explanation: 


Here from circuit,
M_{1} is common-gate amplifier and M_{2} behaves as an active load.
By using properties of common gate (CG) amplifier,
Input impedance \left(R_{i}\right) is low
Output impedance \left(R_{0}\right) is high
So, it is a current amplifier.
Current amplifier is a current controlled current source.
Question 5
For a MOS capacitor, V_{f b} and V_{t} are the flat-band voltage and the threshold voltage, respectively. The variation of the depletion width \left(W_{\text {dep }}\right) for varying gate voltage \left(V_{g}\right) is best represented by

A
A
B
B
C
C
D
D
GATE EC 2023      FET and MOSFET Analysis
Question 5 Explanation: 
\because We know V_{G} \lt V_{F B} then accumulation mode.
\therefore In accumulation mode W_{d}=0 because there is no depletion charge.
Now, V_{F B} \lt V_{G} \lt V_{T} \Rightarrow then depletion and inversion mode.
\therefore Depletion width is available.
\therefore V_{G} \gt V_{T} \Rightarrow Strong inversion.
\therefore Depletion width W_{d} \Rightarrow Constant.
And W_{d}=\sqrt{\frac{2 \epsilon\left|\phi_{S}\right|}{q N_{S}}} and \left|\phi_{S}\right| \propto V_{G}
But after strong inversion, W_{d} remains constant.
\therefore Correction option is (B).




There are 5 questions to complete.