Combinational Circuits

Question 1
Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for A_0,A_1,A_2 \text{ and }A_3 are _______

A
A_0=0,A_1=0,A_2=1,A_3=1
B
A_0=1,A_1=0,A_2=1,A_3=0
C
A_0=0,A_1=1,A_2=1,A_3=0
D
A_0=1,A_1=1,A_2=0,A_3=0
GATE EC 2022   Digital Circuits
Question 1 Explanation: 


f=\bar{C}\bar{D}I_0+\bar{C}DI_1+C\bar{D}I_2+CDI_3
For this
A_0=A_3=0
A_1=A_2=1
Question 2
The figure below shows a multiplexer where S_1 \; and \; S_0 are the select lines, I_0 \; to \; I_3 are the input data lines, EN is the enable line, and F(P, Q, R) is the output, F is
A
PQ+\bar{Q}R
B
P+Q\bar{R}
C
P\bar{Q}R+\bar{P}Q
D
\bar{Q}+PR
GATE EC 2020   Digital Circuits
Question 2 Explanation: 
Output,F=\bar{P}\bar{Q}R+P\bar{Q}R+PQ\, \, \, \,
F=\bar{Q}R+PQ
Question 3
A four-variable Boolean function is realized using 4x1 multiplexers as shown in the figure.
The minimized expression for F(U,V,W, X) is
A
(UV+\bar{U}\bar{V})\bar{W}
B
(UV+\bar{U}\bar{V})(\bar{W}\bar{X}+\bar{W}X)
C
(U\bar{V}+\bar{U}V)\bar{W}
D
(U\bar{V}+\bar{U}V)(\bar{W}\bar{X}+\bar{W}X)
GATE EC 2018   Digital Circuits
Question 3 Explanation: 


Output of the first multiplexer can be expressed as,
F_{1}=\bar{U} V+U \bar{V}
Output of the second multiplexer can be expressed as,
\begin{aligned} F &=\bar{W} \bar{X} F_{1}+\bar{W} X F_{1}=\bar{W} F_{1} \\ &=(\bar{U} V+U \bar{V}) \bar{W} \end{aligned}
Question 4
A programmable logic array (PLA) is shown in the figure.

The Boolean function F implemented is
A
\bar{P}\bar{Q}R + \bar{P}QR + P\bar{Q}\bar{R}
B
(\bar{P}+\bar{Q}+R) (\bar{P}+Q+R) (P+\bar{Q}+\bar{R})
C
\bar{P}\bar{Q}R + \bar{P}QR + P\bar{Q}R
D
(\bar{P}+\bar{Q}+R) (\bar{P}+Q+R) (P+\bar{Q}+R)
GATE EC 2017-SET-2   Digital Circuits
Question 4 Explanation: 
F=\bar{P} \bar{Q} R+\bar{P} Q R+P \bar{Q} R
Question 5
Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to the 4-bit adder are initially reset to

At t=0, the inputs to the 4-bit adder are changed to X_{3}X_{2}X_{1}X_{0}=1100,\; Y_{3}Y_{2}Y_{1}Y_{0}=0100 \; and \; Z_{0}=1. The output of the ripple carry adder will be stable at t (in ns) = ___________
A
60
B
65
C
50
D
75
GATE EC 2017-SET-2   Digital Circuits
Question 5 Explanation: 
In this question inputs to be added are :
\begin{aligned} X_{3} X_{2} X_{1} X_{0}&=1100 \\ Y_{3} Y_{2} Y_{1} Y_{0}&=0100 \text { and } Z_{0}=1 \end{aligned}
For this combination of addition, total minimum delay depends on the addition of most-significant two bits (since least significant two bits are zeros they does not cause any change in Z_{1} and Z_{2}).
So, in the process of addition of given two digits, waveforms at Z_{1} and Z_{2} become stable at t=0 itself.


In the above diagram the waveform at A and B become stable at t = 0 itself, as the applied input combinations does not cause any change.
So, for he given combination of inputs, output will settle at t = 50 ns.
Question 6
Consider the circuit shown in the figure.

The Boolean expression F implemented by the circuit is
A
\bar{X}\bar{Y}\bar{Z}+XY+\bar{Y}Z
B
\bar{X}Y \bar{Z}+XY+\bar{Y}Z
C
\bar{X}Y \bar{Z}+XY+\bar{Y}Z
D
\bar{X}\bar{Y}\bar{Z} +XY+\bar{Y}Z
GATE EC 2017-SET-2   Digital Circuits
Question 6 Explanation: 


\begin{aligned} F_{1} &=\bar{X} Y \\ F &=\bar{Z} F_{1}+Z \bar{F}_{1} \\ &=(\bar{X} Y) \bar{Z}+(\bar{X} Y) Z \\ &=\bar{X} Y \bar{Z}+(X+\bar{Y}) Z \\ F &=\bar{X} Y \bar{Z}+X Z+\bar{Y} Z \end{aligned}
Question 7
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5 ns and 1 ns, respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is __________
A
2
B
4
C
6
D
8
GATE EC 2016-SET-3   Digital Circuits
Question 7 Explanation: 
When, T=\text{logic} 0, the path followed by the circuit would be,
NOR gate \rightarrow \text{MUX} 1 \rightarrow \text{MUX} 2
\Rightarrow 2 \mathrm{ns} \rightarrow 1.5 \mathrm{ns} \rightarrow 1.5 \mathrm{ns}
\Rightarrow 5 \mathrm{ns}
When, T=\text{logic} 1, the path followed by the circuit would be,
NOR gate \rightarrow MUX 1 \rightarrow NOR gate \rightarrow MUX 2
\Rightarrow 1 \mathrm{ns} \rightarrow 1.5 \mathrm{ns} \rightarrow 2 \mathrm{ns} \rightarrow 1.5 \mathrm{ns}
\Rightarrow 6 \mathrm{ns}
\therefore \quad Maximum propagation delay is 6 ns
Question 8
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while C_{in} is the input carry and C_{out} is the output carry. A and B are to be used as the select bits with A being the more significant select bit.

Which one of the following statements correctly describes the choice of signals to be connected to the inputs I_{0},I_{1},I_{2} \; and \; I_{3} so that the output is C_{out}?
A
I_{0}=0,I_{1}=C_{in},I_{2}=C_{in} and I_{3}=1
B
I_{0}=1,I_{1}=C_{in},I_{2}=C_{in} and I_{3}=1
C
I_{0}=C_{in},I_{1}=0,I_{2}=1 and I_{3}=C_{in}
D
I_{0}=0,I_{1}=C_{in},I_{2}=1 and I_{3}=C_{in}
GATE EC 2016-SET-2   Digital Circuits
Question 8 Explanation: 
In case of a full adder,


\begin{aligned} \therefore \quad I_{0}&=0 \\ I_{1}&=C_{\text {in }} \\ I_{2}&=C_{\text {in }} \\ I_{3}&=1 \end{aligned}
Question 9
Identify the circuit below.
A
Binary to Gray code converter
B
Binary to XS3 converter
C
Gray to Binary converter
D
XS3 to Binary converter
GATE EC 2016-SET-1   Digital Circuits
Question 9 Explanation: 
The truth table of the circuit is shown below,
\begin{array}{ccc|ccc} X_{2} & X_{1} & X_{0} & Y_{2} & Y_{1} & Y_{0} \\ \hline 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 & 1 \\ 0 & 1 & 0 & 0 & 1 & 1 \\ 0 & 1 & 1 & 0 & 1 & 0 \\ 1 & 0 & 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 1 & 1 \\ 1 & 1 & 0 & 1 & 0 & 0 \\ 1 & 1 & 1 & 1 & 0 & 1 \end{array}
As Per the truth table none of the options given in the question are correct. However, by making some (minor) changes in the circuit, the answer could be obtained as option (A).
As per GATE official answer Marks to ALL.
Question 10
A 1-to-8 demultiplexer with data input D_{in}, address inputs S_{0}, S_{1}, S_{2} (with S_{0} as the LSB) and \bar{Y}_{0} \; to \; \bar{Y}_7 as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders (with enable E input and address inputs A_{0} \; and \; A_{1}) as shown in the figure. D_{in} , S_{0}, S_{1} \; and \; S_{2} are to be connected to P, Q, R and S, but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be
A
S_{2},D_{in},S_{0},S_{1}
B
S_{1},D_{in},S_{0},S_{2}
C
D_{in},S_{0},S_{1},S_{2}
D
D_{in},S_{2},S_{0},S_{1}
GATE EC 2015-SET-2   Digital Circuits
Question 10 Explanation: 
Consider a 1 \times 8 demultiplexer


\begin{aligned} \text{So,}\quad \bar{Y}_{0} &=\left(\overline{D_{\text {in }} \cdot \bar{S}_{0} \bar{S}_{1} \bar{S}_{2}}\right) \\ \bar{Y}_{0} &=\left(\bar{D}_{\text {in }}+S_{0}+S_{1}+S_{2}\right) \\ \bar{Y}_{1} &=\left(\bar{D}_{\text {in }}+\bar{S}_{0}+S_{1}+S_{2}\right) \\ \bar{Y}_{2} &=\left(\bar{D}_{\text {in }}+S_{0}+\bar{S}_{1}+S_{2}\right) \\ \bar{Y}_{3} &=\left(\bar{D}_{\text {in }}+\bar{S}_{0}+\bar{S}_{1}+S_{2}\right) \\ \bar{Y}_{4} &=\left(\bar{D}_{\text {in }}+S_{0}+S_{1}+\bar{S}_{2}\right) \\ \bar{Y}_{5} &=\left(\bar{D}_{\text {in }}+\bar{S}_{0}+S_{1}+\bar{S}_{2}\right) \\ \bar{Y}_{6} &=\left(\bar{D}_{\text {in }}+S_{0}+\bar{S}_{1}+\bar{S}_{2}\right) \\ \bar{Y}_{7} &=\left(\bar{D}_{\text {in }}+S_{0}+S_{1}+S_{2}\right) \end{aligned}
From the circuit given in question we can see that
\begin{array}{l} \bar{Y}_{0}=\left(1 A_{0}+1 A_{1}+\bar{E}\right) \\ \bar{Y}_{0}=(R+S+P+Q) \end{array}
Similarly,
\bar{Y}_{1}=\left(1 \bar{A}_{0}+1 A_{1}+1 \bar{E}\right)=(P+Q+\bar{R}+S)
\bar{Y}_{4}=\left(2 \bar{A}_{0}+2 A_{1}+2 \bar{E}\right)=(R+S+P+\bar{Q})
So comparing, we get
\begin{array}{l} P={D}_{\text {in }} \\ Q=S_{2} \\ R=S_{1} \\ S=S_{0} \end{array}
There are 10 questions to complete.