Digital Circuits

V_A=\frac{V_R}{2} \; and R_{th}=R
V_B=\frac{V_B}{2}

V_C=\frac{(V_R+V_R/4)}{2}=\frac{5}{8}V_R
R_{th}=2R||2R=R
Similarly,
V_D=\frac{V_C}{2}=\frac{5}{16}V_R
So, \frac{S}{16}V_R=\frac{5}{16} \times 1.6V
V_o=\frac{-3R}{(2R+R)} \times \frac{5}{16} \times 1.6=-\frac{3}{2} \times \frac{5}{16} \times 1.6
V_o=-0.5V

\begin{aligned} y &=A+\bar{B} =\overline{\bar{A}\cdot B}\\ f(A,B)&=A+\bar{B} \\ f(0,B) &=0+\bar{B}=\bar{B}\Rightarrow NOT\; Gate \\ f(A,\bar{B}) &=A+\bar{\bar{B}} =A+B\Rightarrow OR \;Gate\\ f(0,f(A,\bar{B}))&=0+(\overline{A+B})\Rightarrow NOR \; Gate \\ f(\bar{A},B) &= \bar{A}+\bar{B}=\overline{A\cdot B}\Rightarrow NAND\; Gate\\ f(0,f(\bar{A},B))&=0+\overline{\overline{A\cdot B}} =A\cdot B\Rightarrow AND \; Gate \end{aligned}
Since, we can implement NOT Gate we can also implement OR, AND, NOR and NAND Gate.

\left.\begin{matrix} A &\rightarrow &A &P_7 \\ A&\rightarrow &B &P_1 \\ A&\rightarrow &C &P_4 \end{matrix}\right\} \Rightarrow P_1+P_4+P_7=1
\left.\begin{matrix} B &\rightarrow &A &P_2 \\ B&\rightarrow &B &P_3 \end{matrix}\right\} \Rightarrow P_2+P_3=1
\left.\begin{matrix} C &\rightarrow &A &P_6 \\ C&\rightarrow &C &P_5 \end{matrix}\right\} \Rightarrow P_5+P_6=1
P_2+P_3=P_5+P_6\Rightarrow Option (A) is correct.
P_1+P_4+P_7=1\Rightarrow Option (C) is correct.

2-bit counter
\begin{aligned} MSB&&LSB(J,K)\\ 0&&0\\ 0&&1\\ 1&&0\\ 1&&1 \end{aligned}

Duty cycle =50%
Output frequency =f_0/4

(A) NM_H will not be always equal to NM_L because it depends on transistors parameters like size
NM_H=V_{IL}-V_{OL}
NM_L=V_{OH}-V_{IH}
Condition for NM_H=NM_L : when V_{TN}=|V_{TP}|\; and \; V_{IP}=\frac{V_{DD}}{2}
If \frac{K_p}{K_n}< > 1 then NM_H\neq NM_L
(B) Due to capacitive leading of stage, dynamic power consumption during switching will not be zero.
(C) For V_{DD}-|V_{TP}|\leq V_{in}\leq V_{DD} [logic high input]
PMOS \rightarrow cut off
NMOS \rightarrow Linear
(D) Mobility of electrons influences the switching speed because
Propagation delay,
\tau _p=\frac{\tau _{PLH}+P_{PHL}}{2}
\tau _{PLH}=\frac{C_LV_{DD}}{\mu _p C_{ox} \frac{W}{L} (V_{GS}\;\; V_{TP})^2}
\mu _p dependent on mobality
Therefore (C) is only correct.

A. x + z + xy = x(1 + y) + z = x + z
B. (x + y) (x + z) = x + xz + xy + yz = x(1 + y + z) + yz = x + yz
C. x + xy + yz = x(1+y) + yz = x + yz
D. x + xz + xy = x (1 + z + y) = x

f=\bar{C}\bar{D}I_0+\bar{C}DI_1+C\bar{D}I_2+CDI_3
For this
A_0=A_3=0
A_1=A_2=1

\therefore\quad Total 5 clocks required.

Case -1 : when T=0
Propogation delay =t_{AND1}+t_{MUX2}=2+1=3ns

Case -1 : when T=1
Propogation delay =t_{AND2}+t_{MUX1}t_{AND3}+t_{MUX2}=2+1+2+1=6ns

\begin{aligned} \text { Given: } \qquad \qquad V_{p s}&=7.68 \mathrm{~V} \\ n &=8 \mathrm{bit} \\ \text { Resolution }(k) &=\frac{V_{F S}}{2^{n}-1}=\frac{7.68}{2^{8}-1}=0.03\\ \text { Now, } \quad V_{\mathrm{DAC}}&=k \times\{\text { Decimal equivalent }\}\\ &=0.03 \times\{150\} \\ &=4.5 \mathrm{~V} \end{aligned}