# Digital Circuits

 Question 1
In a given sequential circuit, initial states are $Q_{1}=1$ and $Q_{2}=0$. For a clock frequency of $1 \mathrm{MHz}$, the frequency of signal $Q_{2}$ in $\mathrm{kHz}$, is ____
(rounded off to the nearest integer).

 A 200 B 500 C 250 D 750
GATE EC 2023      Sequential Circuits
Question 1 Explanation:
$\begin{array}{|c|c|c|c|c|} \hline Clk & {D}_{\mathbf{1}}=\mathbf{Q}_{\mathbf{2}}[ & D_{\mathbf{2}}=\overline{\mathbf{Q}}_{\mathbf{1}} & {Q}_{\mathbf{1}} & {Q}_{\mathbf{2}} \\ \hline Initial & & & 1 & 0 \\ \hline 1 & 0 & 0 & 0 & 0 \\ 2 & 0 & 1 & 0 & 1 \\ 3 & 1 & 1 & 1 & 1 \\ 4 & 1 & 0 & 1 & 0 \\ \hline \end{array}$
Therefore, the given counter is having MOD-4
$\therefore$ The frequency of signal $Q_{2}=\frac{f_{i}}{4}=\frac{1000}{4} \mathrm{kHz}=250 \mathrm{kHz}$
 Question 2
For the circuit shown below, the propagation delay of each NAND gate is $1 \mathrm{~ns}$. The critical path delay, in ns, is ____ (rounded off to the nearest integer).

 A 1 B 2 C 3 D 4
GATE EC 2023      Logic Gates
Question 2 Explanation:
The given circuit can be drawn as;

$\therefore \quad$ The critical path delay $=1 \mathrm{~ns}+1 \mathrm{~ns}=2 \mathrm{~ns}$

 Question 3
The synchronous sequential circuit shown below works at a clock frequency of $1 \mathrm{GHz}$. The throughput, in $\mathrm{M}$ bits/s, and the latency, in ns, respectively, are

 A $1000,3$ B $333.33,1$ C $2000,3$ D $333.33,3$
GATE EC 2023      Sequential Circuits
Question 3 Explanation:
The given circuit is a type of SISO.
\begin{aligned} \therefore \quad Latency &=n \times T_{\text {clk }} \ldots . .& n= \text{number of flip flops}\\ &=3 \times 1 \quad \ldots . &T_{\mathrm{clk}}=\frac{1}{f_{\mathrm{clk}}}=1 \mathrm{~ns}\\ &=3 \mathrm{~ns} & \end{aligned}
Now,
\begin{aligned} \text{Throughput}&= \text{Number of bits/sec}\\ \because \quad 1 \;bit &=1\; nsec\\ \therefore \quad \text{Throughput} &=10^{9} \mathrm{bits} / \mathrm{sec}\\ &=1000 \mathrm{Mbps} \end{aligned}
 Question 4
In the circuit shown below, $P$ and $Q$ are the inputs. The logical function realized by the circuit shown below is

 A $Y=P Q$ B $Y=P+Q$ C $Y=\overline{P Q}$ D $Y=\overline{P+Q}$
GATE EC 2023      Combinational Circuits
Question 4 Explanation:
\begin{aligned} \text { Output } & =\bar{Q} \cdot I_{0}+Q \cdot I_{1} \\ & =\bar{Q} \cdot 0+Q \cdot P \\ & =P Q \end{aligned}
 Question 5
Consider the circuit shown with an ideal OPAMP. The output voltage $V_o$ is __________V (rounded off to two decimal places).

 A 0.5 B 0.75 C -0.5 D -0.75
GATE EC 2022      ADC and DAC
Question 5 Explanation:

$V_A=\frac{V_R}{2} \; and R_{th}=R$
$V_B=\frac{V_B}{2}$

$V_C=\frac{(V_R+V_R/4)}{2}=\frac{5}{8}V_R$
$R_{th}=2R||2R=R$
Similarly,
$V_D=\frac{V_C}{2}=\frac{5}{16}V_R$
So, $\frac{S}{16}V_R=\frac{5}{16} \times 1.6V$
$V_o=\frac{-3R}{(2R+R)} \times \frac{5}{16} \times 1.6=-\frac{3}{2} \times \frac{5}{16} \times 1.6$
$V_o=-0.5V$

There are 5 questions to complete.