Digital Circuits

For the components in the sequential circuit shown below, t_{pd} is the propagation delay, t_{setup} is the setup time, and t_{hold} is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is ____ MHz.

The state diagram of a sequence detector is shown below. State S_0 is the initial state of the sequence detector. If the output is 1, then

P, Q, and R are the decimal integers corresponding to the 4-bit binary number 1100 considered in signed magnitude, 1's complement, and 2's complement representations, respectively. The 6-bit 2's complement representation of (P+Q+R) is

A 10-bit D/A converter is calibrated over the full range from 0 to 10 V. If the input to the D/A converter is 13A (in hex), the output (rounded off to three decimal places) is _________ V.

The figure below shows a multiplexer where S_1 \; and \; S_0 are the select lines, I_0 \; to \; I_3 are the input data lines, EN is the enable line, and F(P, Q, R) is the output, F is

In the circuits shown, the threshold voltage of each Nmos transistor is 0.6 V. Ignoring the effect of channel length modulation and body bias, the values of Vout1 and Vout2, respectively, in volts, are

The state transition diagram for the circuit shown is

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12?kHz. The frequency of the signal at Q_2 is____ kHz.

In the circuit shown, A and B are the inputs and Fis the output. What is the functionality of the circuit?

In the circuit shown, what are the values of F for EN=0 and EN=1, respectively?