Question 1 |
Consider the circuit shown with an ideal OPAMP. The output voltage V_o is
__________V (rounded off to two decimal places).


0.5 | |
0.75 | |
-0.5 | |
-0.75 |
Question 1 Explanation:

V_A=\frac{V_R}{2} \; and R_{th}=R
V_B=\frac{V_B}{2}

V_C=\frac{(V_R+V_R/4)}{2}=\frac{5}{8}V_R
R_{th}=2R||2R=R
Similarly,
V_D=\frac{V_C}{2}=\frac{5}{16}V_R
So, \frac{S}{16}V_R=\frac{5}{16} \times 1.6V
V_o=\frac{-3R}{(2R+R)} \times \frac{5}{16} \times 1.6=-\frac{3}{2} \times \frac{5}{16} \times 1.6
V_o=-0.5V
Question 2 |
Consider a Boolean gate (D) where the output Y is related to the inputs A and B as,
Y=A+\bar{B} , where + denotes logical OR operation. The Boolean inputs '0' and '1'
are also available separately. Using instances of only D gates and inputs '0' and '1',
__________ (select the correct option(s)).
NAND logic can be implemented | |
OR logic cannot be implemented | |
NOR logic can be implemented | |
AND logic cannot be implemented |
Question 2 Explanation:
\begin{aligned}
y &=A+\bar{B} =\overline{\bar{A}\cdot B}\\
f(A,B)&=A+\bar{B} \\
f(0,B) &=0+\bar{B}=\bar{B}\Rightarrow NOT\; Gate \\
f(A,\bar{B}) &=A+\bar{\bar{B}} =A+B\Rightarrow OR \;Gate\\
f(0,f(A,\bar{B}))&=0+(\overline{A+B})\Rightarrow NOR \; Gate \\
f(\bar{A},B) &= \bar{A}+\bar{B}=\overline{A\cdot B}\Rightarrow NAND\; Gate\\
f(0,f(\bar{A},B))&=0+\overline{\overline{A\cdot B}} =A\cdot B\Rightarrow AND \; Gate
\end{aligned}
Since, we can implement NOT Gate we can also implement OR, AND, NOR and NAND Gate.
Since, we can implement NOT Gate we can also implement OR, AND, NOR and NAND Gate.
Question 3 |
A state transition diagram with states A, B, and C, and transition probabilities p_1,p_2,...,p_7 is shown in the figure (e.g., p_1 denotes the probability of transition from
state A to B). For this state diagram, select the statement(s) which is/are universally
true


p_2+p_3=p_5+p_6 | |
p_1+p_3=p_4+p_6 | |
p_1+p_4+p_7=1 | |
p_2+p_5+p_7=1 |
Question 3 Explanation:
\left.\begin{matrix}
A &\rightarrow &A &P_7 \\
A&\rightarrow &B &P_1 \\
A&\rightarrow &C &P_4
\end{matrix}\right\} \Rightarrow P_1+P_4+P_7=1
\left.\begin{matrix} B &\rightarrow &A &P_2 \\ B&\rightarrow &B &P_3 \end{matrix}\right\} \Rightarrow P_2+P_3=1
\left.\begin{matrix} C &\rightarrow &A &P_6 \\ C&\rightarrow &C &P_5 \end{matrix}\right\} \Rightarrow P_5+P_6=1
P_2+P_3=P_5+P_6\Rightarrow Option (A) is correct.
P_1+P_4+P_7=1\Rightarrow Option (C) is correct.
\left.\begin{matrix} B &\rightarrow &A &P_2 \\ B&\rightarrow &B &P_3 \end{matrix}\right\} \Rightarrow P_2+P_3=1
\left.\begin{matrix} C &\rightarrow &A &P_6 \\ C&\rightarrow &C &P_5 \end{matrix}\right\} \Rightarrow P_5+P_6=1
P_2+P_3=P_5+P_6\Rightarrow Option (A) is correct.
P_1+P_4+P_7=1\Rightarrow Option (C) is correct.
Question 4 |
For the circuit shown, the clock frequency is f_o and the duty cycle is 25%. For the
signal at the Q output of the Flip-Flop, _______.


frequency is f_0/4 and duty cycle is 50% | |
frequency is f_0/4 and duty cycle is 25% | |
frequency is f_0/2 and duty cycle is 50% | |
frequency is f_0 and duty cycle is 25% |
Question 4 Explanation:
2-bit counter
\begin{aligned} MSB&&LSB(J,K)\\ 0&&0\\ 0&&1\\ 1&&0\\ 1&&1 \end{aligned}

Duty cycle =50%
Output frequency =f_0/4
\begin{aligned} MSB&&LSB(J,K)\\ 0&&0\\ 0&&1\\ 1&&0\\ 1&&1 \end{aligned}

Duty cycle =50%
Output frequency =f_0/4
Question 5 |
Select the correct statement(s) regarding CMOS implementation of NOT gates.
Noise Margin High (NM_H) is always equal to the Noise Margin Low (NM_L) irrespective of the sizing of transistors. | |
Dynamic power consumption during switching is zero. | |
For a logical high input under steady state, the nMOSFET is in the linear regime of
operation. | |
Mobility of electrons never influences the switching speed of the NOT gate. |
Question 5 Explanation:
(A) NM_H will not be always equal to NM_L
because it depends on transistors parameters
like size
NM_H=V_{IL}-V_{OL}
NM_L=V_{OH}-V_{IH}
Condition for NM_H=NM_L : when V_{TN}=|V_{TP}|\; and \; V_{IP}=\frac{V_{DD}}{2}
If \frac{K_p}{K_n}< > 1 then NM_H\neq NM_L
(B) Due to capacitive leading of stage, dynamic power consumption during switching will not be zero.
(C) For V_{DD}-|V_{TP}|\leq V_{in}\leq V_{DD} [logic high input]
PMOS \rightarrow cut off
NMOS \rightarrow Linear
(D) Mobility of electrons influences the switching speed because
Propagation delay,
\tau _p=\frac{\tau _{PLH}+P_{PHL}}{2}
\tau _{PLH}=\frac{C_LV_{DD}}{\mu _p C_{ox} \frac{W}{L} (V_{GS}\;\; V_{TP})^2}
\mu _p dependent on mobality
Therefore (C) is only correct.
NM_H=V_{IL}-V_{OL}
NM_L=V_{OH}-V_{IH}
Condition for NM_H=NM_L : when V_{TN}=|V_{TP}|\; and \; V_{IP}=\frac{V_{DD}}{2}
If \frac{K_p}{K_n}< > 1 then NM_H\neq NM_L
(B) Due to capacitive leading of stage, dynamic power consumption during switching will not be zero.
(C) For V_{DD}-|V_{TP}|\leq V_{in}\leq V_{DD} [logic high input]
PMOS \rightarrow cut off
NMOS \rightarrow Linear
(D) Mobility of electrons influences the switching speed because
Propagation delay,
\tau _p=\frac{\tau _{PLH}+P_{PHL}}{2}
\tau _{PLH}=\frac{C_LV_{DD}}{\mu _p C_{ox} \frac{W}{L} (V_{GS}\;\; V_{TP})^2}
\mu _p dependent on mobality
Therefore (C) is only correct.
Question 6 |
Select the Boolean function(s) equivalent to x+yz, where x,y, and z are Boolean
variables, and + denotes logical OR operation.
x+z+xy | |
(x+y)(x+z) | |
x+xy+yz | |
x+xz+xy |
Question 6 Explanation:
A. x + z + xy = x(1 + y) + z = x + z
B. (x + y) (x + z) = x + xz + xy + yz = x(1 + y + z) + yz = x + yz
C. x + xy + yz = x(1+y) + yz = x + yz
D. x + xz + xy = x (1 + z + y) = x
B. (x + y) (x + z) = x + xz + xy + yz = x(1 + y + z) + yz = x + yz
C. x + xy + yz = x(1+y) + yz = x + yz
D. x + xz + xy = x (1 + z + y) = x
Question 7 |
Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the
XOR of C and D, the values for A_0,A_1,A_2 \text{ and }A_3 are _______


A_0=0,A_1=0,A_2=1,A_3=1 | |
A_0=1,A_1=0,A_2=1,A_3=0 | |
A_0=0,A_1=1,A_2=1,A_3=0 | |
A_0=1,A_1=1,A_2=0,A_3=0 |
Question 7 Explanation:

f=\bar{C}\bar{D}I_0+\bar{C}DI_1+C\bar{D}I_2+CDI_3
For this
A_0=A_3=0
A_1=A_2=1
Question 8 |
The propagation delay of the exclusive-\text{OR} (\text{XOR})
gate in the circuit in the figure is 3\:ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (\text{Clk})
frequency provided to the circuit is 500\: \text{MHz}.

Starting from the initial value of the flip-flop outputs Q_{2}Q_{1}Q_{0} = 1\;1\;1 with D_{2}=1, the minimum number of triggering clock edges after which the flip-flop outputs Q_{2}Q_{1}Q_{0} becomes 1\; 0\; 0 (in integer) is

Starting from the initial value of the flip-flop outputs Q_{2}Q_{1}Q_{0} = 1\;1\;1 with D_{2}=1, the minimum number of triggering clock edges after which the flip-flop outputs Q_{2}Q_{1}Q_{0} becomes 1\; 0\; 0 (in integer) is
3 | |
4 | |
5 | |
6 |
Question 8 Explanation:

\therefore\quad Total 5 clocks required.
Question 9 |
The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in the circuit shown in the figure are 4 ns, 2 ns and 1 ns, respectively.

If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is

If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is
3 ns | |
5 ns | |
6 ns | |
7 ns |
Question 9 Explanation:
Case -1 : when T=0
Propogation delay =t_{AND1}+t_{MUX2}=2+1=3ns
Case -1 : when T=1
Propogation delay =t_{AND2}+t_{MUX1}t_{AND3}+t_{MUX2}=2+1+2+1=6ns
Propogation delay =t_{AND1}+t_{MUX2}=2+1=3ns
Case -1 : when T=1
Propogation delay =t_{AND2}+t_{MUX1}t_{AND3}+t_{MUX2}=2+1+2+1=6ns
Question 10 |
An 8-bit unipolar (all analog output values are positive) digital-to-analog converter (DAC) has a full-scale voltage range from 0\; V
to 7.68\:V. If the digital input code is 10010110
(the leftmost bit is \text{MSB}), then the analog output voltage of the DAC (rounded off to one decimal place) is ___________ V.
2.4 | |
4.5 | |
8.4 | |
5.4 |
Question 10 Explanation:
\begin{aligned} \text { Given: } \qquad \qquad V_{p s}&=7.68 \mathrm{~V} \\ n &=8 \mathrm{bit} \\ \text { Resolution }(k) &=\frac{V_{F S}}{2^{n}-1}=\frac{7.68}{2^{8}-1}=0.03\\ \text { Now, } \quad V_{\mathrm{DAC}}&=k \times\{\text { Decimal equivalent }\}\\ &=0.03 \times\{150\} \\ &=4.5 \mathrm{~V} \end{aligned}
There are 10 questions to complete.