Digital Circuits

Question 1
For the components in the sequential circuit shown below, t_{pd} is the propagation delay, t_{setup} is the setup time, and t_{hold} is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is ____ MHz.
A
76.92
B
46.23
C
85.12
D
121.23
GATE EC 2020      Sequential Circuits
Question 1 Explanation: 
Total propagation delay =(t_{pd}+t_{set-up})_{max}=8ns+5ns=13ns
\therefore Frequency of operations =\frac{1000}{13}MHz=76.92MHz
Question 2
The state diagram of a sequence detector is shown below. State S_0 is the initial state of the sequence detector. If the output is 1, then
A
the sequence 01010 is detected
B
the sequence 01011 is detected
C
the sequence 01110 is detected
D
the sequence 01001 is detected
GATE EC 2020      Sequential Circuits
Question 3
P, Q, and R are the decimal integers corresponding to the 4-bit binary number 1100 considered in signed magnitude, 1's complement, and 2's complement representations, respectively. The 6-bit 2's complement representation of (P+Q+R) is
A
110101
B
110010
C
111101
D
111001
GATE EC 2020      Number Systems
Question 3 Explanation: 
Given, binary number 1100
1's complement of 1100 = -3
Sign magnitude of 1100 = -4
2's complement of 1100 = -4
P + Q + R = -4 - 3 - 4 = -11
The 6 digit 2's complement of (-11) = 110101
Question 4
A 10-bit D/A converter is calibrated over the full range from 0 to 10 V. If the input to the D/A converter is 13A (in hex), the output (rounded off to three decimal places) is _________ V.
A
3.069
B
1.214
C
2.124
D
0.257
GATE EC 2020      ADC and DAC
Question 4 Explanation: 
Given, n=10
V_{FS}=10\, V
Input Voltage=(13A)_{16}=(314)_{10}
Output Voltage=Resolution X Decimal Equivalent of input
V_{o}=\frac{10}{2^{10}-1}\times 314=3.069\, V
Question 5
The figure below shows a multiplexer where S_1 \; and \; S_0 are the select lines, I_0 \; to \; I_3 are the input data lines, EN is the enable line, and F(P, Q, R) is the output, F is
A
PQ+\bar{Q}R
B
P+Q\bar{R}
C
P\bar{Q}R+\bar{P}Q
D
\bar{Q}+PR
GATE EC 2020      Combinational Circuits
Question 5 Explanation: 
Output,F=\bar{P}\bar{Q}R+P\bar{Q}R+PQ\, \, \, \,
F=\bar{Q}R+PQ
Question 6
In the circuits shown, the threshold voltage of each Nmos transistor is 0.6 V. Ignoring the effect of channel length modulation and body bias, the values of Vout1 and Vout2, respectively, in volts, are
A
1.8 and 1.2
B
2.4 and 2.4
C
1.8 and 2.4
D
2.4 and 1.2
GATE EC 2019      Logic Families
Question 6 Explanation: 


V_{\text {out } 1}=3-0.6-0.6=1.8 \mathrm{V}

Question 7
The state transition diagram for the circuit shown is
A
A
B
B
C
C
D
D
GATE EC 2019      Finite State Machine and Miscellaneous
Question 7 Explanation: 
When A=0, Q_{n+1}=1
When A=1, Q_{n+1}=\bar{Q}_{n}
So, the correct state transition diagram is,

Question 8
In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12?kHz. The frequency of the signal at Q_2 is____ kHz.
A
2
B
4
C
6
D
8
GATE EC 2019      Sequential Circuits
Question 8 Explanation: 


\begin{aligned} M O D &=3 \\ f_{Q 2} &=\frac{f_{c \mid k}}{3}=\frac{12}{3} k H z=4 k H z \end{aligned}
Question 9
In the circuit shown, A and B are the inputs and Fis the output. What is the functionality of the circuit?
A
Latch
B
XNOR
C
SRAM Cell
D
XOR
GATE EC 2019      Logic Families
Question 9 Explanation: 




So, the given logic circuit acts as an XNOR gate
Question 10
In the circuit shown, what are the values of F for EN=0 and EN=1, respectively?
A
0 and D
B
Hi-Z and D
C
0 and 1
D
Hi-Z and \bar{D}
GATE EC 2019      Logic Families
Question 10 Explanation: 


When E N=0
x_{1}=(\overline{D \cdot 0})=1 \Rightarrow PMOS is in OFF state
x_{2}=(\overline{1+D})=0 \Rightarrow NMOS is in OFF state
Both the transistors are in OFF state, which offers high impedance.
\begin{aligned} \text { When } E N=1: x_{1}&=(\overline{D \cdot 1})=\bar{D} \\ x_{2}&=(\overline{0+D})=\bar{D} \\ F &=D \end{aligned}


There are 10 questions to complete.
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