FET and MOSFET Analysis

Question 1
Consider the circuit shown with an ideal long channel nMOSFET (enhancementmode, substrate is connected to the source). The transistor is appropriately biased in the saturation region with V_{GG} and V_{DD} such that it acts as a linear amplifier. v_i is the small-signal ac input voltage. v_A and v_B represent the small-signal voltages at the nodes A and B, respectively. The value of \frac{v_A}{v_B} is ________ (rounded off to one decimal place).

A
-2
B
2
C
-1
D
1
GATE EC 2022   Analog Circuits
Question 1 Explanation: 
For ac analysis

\begin{aligned} V_A &=-i_d\cdot 4k \\ V_B&=i_d\cdot 2k \\ \frac{V_A}{V_B}&=\frac{-4}{2} \\ \frac{V_A}{V_B}&=-2 \end{aligned}
Question 2
Consider an ideal long channel nMOSFET (enhancement-mode) with gate length 10\mu m and width 100\mu m. The product of electron mobility ( \mu _n) and oxide capacitance per unit area ( C_{OX}) is \mu _n C_{OX}=1mA/V^2. The threshold voltage of the transistor is 1 V. For a gate-to-source voltage V_{GS}=[2-\sin (2t)]V and drain-tosource voltage V_{DS}=1V (substrate connected to the source), the maximum value of the drain-to-source current is ________.
A
40 mA
B
20 mA
C
15 mA
D
5 mA
GATE EC 2022   Analog Circuits
Question 2 Explanation: 
\mu _n Co_x=1mA/V^2; W=100\mu m;L=10\mu m
V_T= \perp V; V_{GS}=[2-\sin 2t]V;V_{DS}=1V

Let,
\begin{aligned} V_{GS} &=3V(max)\\ \Rightarrow V_{DS} &\lt V_{GS}-V_t\\ \because \; 1 &\lt (3-1) \end{aligned}
MOSFET in triode region
\begin{aligned} I_{Dmax}&=\mu _CO_x\left ( \frac{\omega }{L} \right )\left \{ \left ( V_{as \; max}-V_t \right )V_{DS}-\frac{1}{2}V_{DS}^2 \right \}\\ &=1 \times \left ( \frac{100}{10} \right )\left \{ (3-1) \times 1-\frac{1}{2} \times 1^2 \right \}mA\\ &=10(2-1/2)\\ &=15mA \end{aligned}
Question 3
The ideal long channel nMOSFET and pMOSFET devices shown in the circuits have threshold voltages of 1 V and -1 V, respectively. The MOSFET substrates are connected to their respective sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady state voltages are ______

A
V_1=5 V, V_2=5 V
B
V_1=5 V, V_2=4 V
C
V_1=4 V, V_2=5 V
D
V_1=4V, V_2=-5 V
GATE EC 2022   Analog Circuits
Question 3 Explanation: 


Question 4
Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width (W) to gate length (L) ratios \frac{W}{L} of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the pMOSFET, the threshold voltage is -1 V and the mobility of holes is 40\frac{cm^2}{V.s}. For the nMOSFET, the threshold voltage is 1 V and the mobility of electrons is 300\frac{cm^2}{V.s}. The steady state output voltage V_o is ________.

A
equal to 0 V
B
more than 2 V
C
less than 2 V
D
equal to 2 V
GATE EC 2022   Analog Circuits
Question 4 Explanation: 


\begin{aligned} \mu _PCO_x\left ( \frac{\omega }{L} \right )_1[4-V_0-1]^2&=\mu _nCO_x\left ( \frac{\omega }{L} \right )_2[V_0-0-1]^2\\ \Rightarrow \frac{300}{40}\times \frac{1}{5}(V_0-1)^2&=(3-V_0)^2\\ \Rightarrow \sqrt{1.5} (V_0-1)&=3-V_0\\ \Rightarrow V_0&=\frac{3+\sqrt{1.5}}{\sqrt{1.5}+1} \lt 2V \end{aligned}
Question 5
Using the incremental low frequency small-signal model of the MOS device, the Norton equivalent resistance of the following circuit is
A
r_{ds}+R+g_mr_{ds}R
B
\frac{r_{ds} +R}{1+g_m r_{ds}}
C
r_{ds}+\frac{1}{g_m}+R
D
r_{ds}+R
GATE EC 2020   Analog Circuits
Question 5 Explanation: 
\begin{aligned}v_{\pi }&=-V_{x} \\ V_{x}&=\left ( I_{x}-g_{m}V_{x} \right )r_{ds}+I_{x}R\\ V_{x}\left ( 1+g_{m} r_{ds}\right )&=\left ( r_{ds}+R \right )I_{x} \\ R_{N}&=\frac{V_{x}}{I_{x}}=\frac{R+r_{ds}}{1+g_{m}r_{ds}}\end{aligned}

Question 6
An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to -10 V. If the input voltage V_I lies between \pm 10 V, the minimum and the maximum values of V_G required for proper sampling and holding respectively, are
A
3V and -3 V
B
10 V and -10 V
C
13 V and -7 V
D
10 V and -13 V
GATE EC 2020   Analog Circuits
Question 6 Explanation: 

for holding MOSFET should be OFF.
\begin{aligned}V_{1\, min}&\rightarrow -10\, V \\ V_{G}-V_{1\, min}& \lt 3 \\ V_{G}& \lt 3-10V\Rightarrow -7V \\ \text{For Sampling, } V_{G}-V_{i\, max}& \gt 3\\ V_{G}& \gt 3+V_{i\, max}\\ V_{G}&\gt 13\end{aligned}
Question 7
In the circuit shown, V_1=0 \; and \; V_2=V_{dd}. The other relevant parameters are mentioned in the figure. Ignoring the effect of channel length modulation and the body effect, the value of I_{out} is _____mA(rounded off to 1 decimal place).
A
4.2
B
6
C
8.3
D
2.4
GATE EC 2019   Analog Circuits
Question 7 Explanation: 


\begin{aligned} \frac{I_{2}}{I_{1}} &=\frac{(W / L)_{2}}{(W / L)_{1}}=\frac{3}{2} \\ I_{2} &=\frac{3}{2} \times I_{1}=1.5 \mathrm{mA} \end{aligned}
M_{3} is OFF because V_{1}=0 \Rightarrow I_{3}=0
M_{4} is ON because V_{2}=V_{D D}
\begin{aligned} I_{5} &=I_{4}=I_{2}=1.5 \mathrm{mA} \\ \frac{I_{6}}{I_{5}} &=\frac{(W / L)_{6}}{(W / L)_{5}}=\frac{40}{10}=4 \\ I_{6} &=4 I_{5}=4 \times 1.5=6 \mathrm{mA} \\ \therefore \quad I_{\text {out }} &=I_{6}=6 \mathrm{mA} \end{aligned}
Question 8
In the circuit shown, the threshold voltages of the pMOS (|V_{tp}|) and nMOS (V_{tn}) transistors are both equal to 1 V. All the transistors have the same output resistance r_{ds} of 6 M\Omega. The other parameters are listed below:

\mu_n C_{ox}=60\mu A/V^2; \left ( \frac{W}{L} \right )_{nMOS}=5
\mu_p C_{ox}=30\mu A/V^2; \left ( \frac{W}{L} \right )_{pMOS}=10

\mu_n \; and \; \mu_p are the carrier mobilities, and C_{ox} is the oxide capacitance per unit area. Ignoring the effect of channel length modulation and body bias, the gain of the circuit is____ (rounded off to 1 decimal place).
A
-800
B
-750.6
C
-900
D
-652.3
GATE EC 2019   Analog Circuits
Question 8 Explanation: 
M_{3} and M_{4} are identical PMOS transistor and they have equal current.
Hence their V_{SG} should be equal.


\begin{aligned} V_{S G 3} &=V_{S G 4}=\frac{V_{D D}}{2}=2 V \\ I_{S D} &=\frac{\mu_{p} C_{o x}}{2}\left(\frac{W}{L}\right)_{p}\left(V_{S G}-\left|V_{T}\right|\right)^{2} \\ &=\frac{30}{2} \times 10(2-1)^{2}=150 \mu \mathrm{A} \end{aligned}
now, by using current mirror property all transistor should have equal current.
\begin{aligned} I_{\mathrm{DSN}}&=I_{\mathrm{SDP}}=150 \mu \mathrm{A} \\ \text { For } M_{1} \quad g_{m 1}&=\sqrt{2 \mu_{n} C_{o x} \frac{W}{L} \times I_{D S}} \\ &=\sqrt{2 \mu_{n} C_{0 x}} \frac{W}{L} \times I_{D S}\\ & =\sqrt{2 \times 60 \times 5 \times 150}=300 \mathrm{m} \end{aligned}
M_{2}, M_{3} and M_{4} from active load for M_{1}. This active load in equivalent to resistance r_{d s 2} i.e. 6 \mathrm{M} \Omega


M_{1} is common source amplifier.
\begin{aligned} \therefore \quad \frac{V_{\text {out }}}{V_{\text {in }}} &=A_{v}=-g_{m 1} \times\left(r_{\text {ds2 }} \| r_{\text {ds1 }}\right) \\ &=-300 \mathrm{M} \mathrm{C} \times 3 \mathrm{M} \Omega=-900 \end{aligned}
Question 9
A CMOS inverter, designed to have a mid-point voltage V_I equal to half of V_{dd}, as shown in the figure, has the following parameters:

V_{dd}=3V
\mu_n C_{ox}=100\mu A/V^2; V_{tn}=0.7 V for nMOS
\mu_p C_{ox}=40\mu A/V^2; |V_{tp}|=0.9 V for pMOS

The ratio of \left ( \frac{W}{L} \right )_n to \left ( \frac{W}{L} \right )_p is equal to ____(rounded off to 3 decimal places).
A
0.225
B
0.124
C
0.324
D
0.624
GATE EC 2019   Analog Circuits
Question 9 Explanation: 
I_{D n}=I_{D p} and both will be in saturation
\begin{aligned} \text{If }\quad V_{\mathrm{IN}}&=\frac{V_{D D}}{2}=1.5 \mathrm{V}=V_{\mathrm{GSN}}=V_{S G P} \\ \Rightarrow \frac{1}{2}&\left(\mu_{n} C_{O x}\right)\left(\frac{W}{L}\right)_{n}\left[V_{\mathrm{GSN}}-V_{T N}\right]^{2} \\ =& \frac{1}{2}\left(\mu_{p} C_{Q x}\right)\left(\frac{W}{L}\right)_{p}\left[V_{G S P}+V_{T P}\right]^{2} \\ 100 \times 10^{-6}\left(\frac{W}{L}\right)_{n} &[1.5-0.7]^{2} \\ &=40 \times 10^{-6}\left(\frac{W}{L}\right)_{p}[1.5-0.9]^{2} \\ \Rightarrow \quad \frac{\left(\frac{W}{L}\right)_{n}}{\left(\frac{W}{L}\right)_{p}}&=\frac{40}{100} \times \frac{(0.6)^{2}}{(0.8)^{2}}=0.225 \end{aligned}
Question 10
In the circuit shown below, the (W/L) value for M_{2} is twice that for M_{1} . The two nMOS transistors are otherwise identical. The threshold voltage V_{T} for both transistors is 1.0V. Note that V_{GS} \; for M_{2} must be \gt 1.0 V.
The voltage (in volts, accurate to two decimal places) at V_{x} is _______.
A
0.33
B
0.42
C
0.55
D
0.75
GATE EC 2018   Analog Circuits
Question 10 Explanation: 
\begin{aligned} \text{Let},\quad K_{n}&=\frac{\mu_{n} C_{o x}}{2}\left(\frac{W}{L}\right)\\ \text{Given that,}\\ \left(\frac{W}{L}\right)_{2} &=2\left(\frac{W}{L}\right)_{1} \\ \text{So,}\quad K_{n 2} &=2 K_{n 1}\\ \text{For }M_{1}, \quad V_{G S 1}-V_{T}&=2-1=1 V \\ \text{For }M_{2}, \quad V_{G S 2}-V_{T}&=2-V_{x}-1=1 \mathrm{V}-V_{x}<1 \mathrm{V} \\ V_{D S 2}&=\left(3.3-V_{x}\right)>\left(V_{G S 2}-V_{T}\right) \end{aligned}
So, M_{1} will be in linear region and M_{2} will be in saturation region.
\begin{aligned} I_{D_{1}}&=I_{D_{2}} \\ K_{n 1}\left[2\left(V_{G S 1}-V_{T}\right) V_{D S 1}-V_{D S 1}^{2}\right]&=K_{n 2}\left(V_{G S 2}-V_{T}\right)^{2} \\ K_{n 1}\left[2(2-1) V_{x}-V_{x}^{2}\right]&=2 K_{n 1}\left(2-V_{x}-1\right)^{2} \\ 2 V_{x}-V_{x}^{2} &=2\left(1+V_{x}^{2}-2 V_{x}\right) \\ &=2 V_{x}^{2}-4 V_{x}+2\\ 3V_{x}^{2}-6 V_{x}+2 &=0 \\ V_{x}^{2}-2 V_{x}+\frac{2}{3} &=0 \\ V_{x} &=1 \pm \sqrt{\frac{4-\frac{8}{3}}{4}}=1 \pm \sqrt{\frac{1}{3}} V \\ V_{GS2}&=\left(2-V_{x}\right) \geq V_{T}\\ \Rightarrow \quad \left(1-V_{x}\right) &\geq0\\ \text{So, valid value,} \quad V_{x}&=1-\sqrt{\frac{1}{3}}=0.4226 \mathrm{V} \end{aligned}
There are 10 questions to complete.