# FET and MOSFET Analysis

 Question 1
Using the incremental low frequency small-signal model of the MOS device, the Norton equivalent resistance of the following circuit is
 A $r_{ds}+R+g_mr_{ds}R$ B $\frac{r_{ds} +R}{1+g_m r_{ds}}$ C $r_{ds}+\frac{1}{g_m}+R$ D $r_{ds}+R$
GATE EC 2020   Analog Circuits
Question 1 Explanation:
\begin{aligned}v_{\pi }&=-V_{x} \\ V_{x}&=\left ( I_{x}-g_{m}V_{x} \right )r_{ds}+I_{x}R\\ V_{x}\left ( 1+g_{m} r_{ds}\right )&=\left ( r_{ds}+R \right )I_{x} \\ R_{N}&=\frac{V_{x}}{I_{x}}=\frac{R+r_{ds}}{1+g_{m}r_{ds}}\end{aligned}

 Question 2
An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to -10 V. If the input voltage $V_I$ lies between $\pm 10$ V, the minimum and the maximum values of $V_G$ required for proper sampling and holding respectively, are
 A 3V and -3 V B 10 V and -10 V C 13 V and -7 V D 10 V and -13 V
GATE EC 2020   Analog Circuits
Question 2 Explanation:

for holding MOSFET should be OFF.
\begin{aligned}V_{1\, min}&\rightarrow -10\, V \\ V_{G}-V_{1\, min}& \lt 3 \\ V_{G}& \lt 3-10V\Rightarrow -7V \\ \text{For Sampling, } V_{G}-V_{i\, max}& \gt 3\\ V_{G}& \gt 3+V_{i\, max}\\ V_{G}&\gt 13\end{aligned}
 Question 3
In the circuit shown, $V_1=0 \; and \; V_2=V_{dd}$. The other relevant parameters are mentioned in the figure. Ignoring the effect of channel length modulation and the body effect, the value of $I_{out}$ is _____mA(rounded off to 1 decimal place).
 A 4.2 B 6 C 8.3 D 2.4
GATE EC 2019   Analog Circuits
Question 3 Explanation:

\begin{aligned} \frac{I_{2}}{I_{1}} &=\frac{(W / L)_{2}}{(W / L)_{1}}=\frac{3}{2} \\ I_{2} &=\frac{3}{2} \times I_{1}=1.5 \mathrm{mA} \end{aligned}
$M_{3}$ is OFF because $V_{1}=0 \Rightarrow I_{3}=0$
$M_{4}$ is ON because $V_{2}=V_{D D}$
\begin{aligned} I_{5} &=I_{4}=I_{2}=1.5 \mathrm{mA} \\ \frac{I_{6}}{I_{5}} &=\frac{(W / L)_{6}}{(W / L)_{5}}=\frac{40}{10}=4 \\ I_{6} &=4 I_{5}=4 \times 1.5=6 \mathrm{mA} \\ \therefore \quad I_{\text {out }} &=I_{6}=6 \mathrm{mA} \end{aligned}
 Question 4
In the circuit shown, the threshold voltages of the pMOS (|$V_{tp}$|) and nMOS ($V_{tn}$) transistors are both equal to 1 V. All the transistors have the same output resistance $r_{ds}$ of 6 M$\Omega$. The other parameters are listed below:

$\mu_n C_{ox}=60\mu A/V^2$; $\left ( \frac{W}{L} \right )_{nMOS}=5$
$\mu_p C_{ox}=30\mu A/V^2$; $\left ( \frac{W}{L} \right )_{pMOS}=10$

$\mu_n \; and \; \mu_p$ are the carrier mobilities, and $C_{ox}$ is the oxide capacitance per unit area. Ignoring the effect of channel length modulation and body bias, the gain of the circuit is____ (rounded off to 1 decimal place).
 A -800 B -750.6 C -900 D -652.3
GATE EC 2019   Analog Circuits
Question 4 Explanation:
$M_{3}$ and $M_{4}$ are identical PMOS transistor and they have equal current.
Hence their $V_{SG}$ should be equal.

\begin{aligned} V_{S G 3} &=V_{S G 4}=\frac{V_{D D}}{2}=2 V \\ I_{S D} &=\frac{\mu_{p} C_{o x}}{2}\left(\frac{W}{L}\right)_{p}\left(V_{S G}-\left|V_{T}\right|\right)^{2} \\ &=\frac{30}{2} \times 10(2-1)^{2}=150 \mu \mathrm{A} \end{aligned}
now, by using current mirror property all transistor should have equal current.
\begin{aligned} I_{\mathrm{DSN}}&=I_{\mathrm{SDP}}=150 \mu \mathrm{A} \\ \text { For } M_{1} \quad g_{m 1}&=\sqrt{2 \mu_{n} C_{o x} \frac{W}{L} \times I_{D S}} \\ &=\sqrt{2 \mu_{n} C_{0 x}} \frac{W}{L} \times I_{D S}\\ & =\sqrt{2 \times 60 \times 5 \times 150}=300 \mathrm{m} \end{aligned}
$M_{2}, M_{3}$ and $M_{4}$ from active load for $M_{1}$. This active load in equivalent to resistance $r_{d s 2} i.e. 6 \mathrm{M} \Omega$

$M_{1}$ is common source amplifier.
\begin{aligned} \therefore \quad \frac{V_{\text {out }}}{V_{\text {in }}} &=A_{v}=-g_{m 1} \times\left(r_{\text {ds2 }} \| r_{\text {ds1 }}\right) \\ &=-300 \mathrm{M} \mathrm{C} \times 3 \mathrm{M} \Omega=-900 \end{aligned}
 Question 5
A CMOS inverter, designed to have a mid-point voltage $V_I$ equal to half of $V_{dd}$, as shown in the figure, has the following parameters:

$V_{dd}$=3V
$\mu_n C_{ox}=100\mu A/V^2$; $V_{tn}=0.7 V$ for nMOS
$\mu_p C_{ox}=40\mu A/V^2$; $|V_{tp}|=0.9 V$ for pMOS

The ratio of $\left ( \frac{W}{L} \right )_n$ to $\left ( \frac{W}{L} \right )_p$ is equal to ____(rounded off to 3 decimal places).
 A 0.225 B 0.124 C 0.324 D 0.624
GATE EC 2019   Analog Circuits
Question 5 Explanation:
$I_{D n}=I_{D p}$ and both will be in saturation
\begin{aligned} \text{If }\quad V_{\mathrm{IN}}&=\frac{V_{D D}}{2}=1.5 \mathrm{V}=V_{\mathrm{GSN}}=V_{S G P} \\ \Rightarrow \frac{1}{2}&\left(\mu_{n} C_{O x}\right)\left(\frac{W}{L}\right)_{n}\left[V_{\mathrm{GSN}}-V_{T N}\right]^{2} \\ =& \frac{1}{2}\left(\mu_{p} C_{Q x}\right)\left(\frac{W}{L}\right)_{p}\left[V_{G S P}+V_{T P}\right]^{2} \\ 100 \times 10^{-6}\left(\frac{W}{L}\right)_{n} &[1.5-0.7]^{2} \\ &=40 \times 10^{-6}\left(\frac{W}{L}\right)_{p}[1.5-0.9]^{2} \\ \Rightarrow \quad \frac{\left(\frac{W}{L}\right)_{n}}{\left(\frac{W}{L}\right)_{p}}&=\frac{40}{100} \times \frac{(0.6)^{2}}{(0.8)^{2}}=0.225 \end{aligned}
 Question 6
In the circuit shown below, the (W/L) value for $M_{2}$ is twice that for $M_{1}$. The two nMOS transistors are otherwise identical. The threshold voltage $V_{T}$ for both transistors is 1.0V. Note that $V_{GS} \; for M_{2}$ must be $\gt$ 1.0 V.
The voltage (in volts, accurate to two decimal places) at $V_{x}$ is _______.
 A 0.33 B 0.42 C 0.55 D 0.75
GATE EC 2018   Analog Circuits
Question 6 Explanation:
\begin{aligned} \text{Let},\quad K_{n}&=\frac{\mu_{n} C_{o x}}{2}\left(\frac{W}{L}\right)\\ \text{Given that,}\\ \left(\frac{W}{L}\right)_{2} &=2\left(\frac{W}{L}\right)_{1} \\ \text{So,}\quad K_{n 2} &=2 K_{n 1}\\ \text{For }M_{1}, \quad V_{G S 1}-V_{T}&=2-1=1 V \\ \text{For }M_{2}, \quad V_{G S 2}-V_{T}&=2-V_{x}-1=1 \mathrm{V}-V_{x}<1 \mathrm{V} \\ V_{D S 2}&=\left(3.3-V_{x}\right)>\left(V_{G S 2}-V_{T}\right) \end{aligned}
So, $M_{1}$ will be in linear region and $M_{2}$ will be in saturation region.
\begin{aligned} I_{D_{1}}&=I_{D_{2}} \\ K_{n 1}\left[2\left(V_{G S 1}-V_{T}\right) V_{D S 1}-V_{D S 1}^{2}\right]&=K_{n 2}\left(V_{G S 2}-V_{T}\right)^{2} \\ K_{n 1}\left[2(2-1) V_{x}-V_{x}^{2}\right]&=2 K_{n 1}\left(2-V_{x}-1\right)^{2} \\ 2 V_{x}-V_{x}^{2} &=2\left(1+V_{x}^{2}-2 V_{x}\right) \\ &=2 V_{x}^{2}-4 V_{x}+2\\ 3V_{x}^{2}-6 V_{x}+2 &=0 \\ V_{x}^{2}-2 V_{x}+\frac{2}{3} &=0 \\ V_{x} &=1 \pm \sqrt{\frac{4-\frac{8}{3}}{4}}=1 \pm \sqrt{\frac{1}{3}} V \\ V_{GS2}&=\left(2-V_{x}\right) \geq V_{T}\\ \Rightarrow \quad \left(1-V_{x}\right) &\geq0\\ \text{So, valid value,} \quad V_{x}&=1-\sqrt{\frac{1}{3}}=0.4226 \mathrm{V} \end{aligned}
 Question 7
Two identical nMOS transistors $M_{1}$ and $M_{2}$ are connected as shown below. The circuit is used as an amplifier with the input connected between G and S terminals and the output taken between D and S terminals. $V_{bias}$ and $V_{D}$ are so adjusted that both transistors are in saturation. The transconductance of this combination is defined as $g_{m}=\frac{\partial i_{D}}{\partial V_{GS}}$ while the output resistance is $r_{0}=\frac{\partial V_{GS}}{\partial i_{D}}$ , where $i_{D}$ is the current flowing into the drain of $M_{2}$. Let $g_{m1}$ , $g_{m2}$ be the transconductances and $r_{01}$ , $r_{02}$ be the output resistances of transistors $M_{1}$ and $M_{2}$ , respectively.

Which of the following statements about estimates for $g_{m}$ and $r_{0}$ is correct?
 A $g_{m}\approx g_{m1}\cdot g_{m2}\cdot r_{02} \;and \; r_0 \approx r_{01}+r_{02}.$ B $g_{m}\approx g_{m1}\ + g_{m2} \; and \; r_{0} \approx r_{01}+r_{02}.$ C $g_{m}\approx g_{m1} \; and \; r_{0}\approx r_{01} \cdot g_{m2}\cdot r_{02}.$ D $g_{m}\approx g_{m1} \; and \; r_{0}\approx r_{02}$.
GATE EC 2018   Analog Circuits
Question 7 Explanation:

$g_{m}=\frac{\Delta I_{D}}{\Delta V_{\text {in }}}=\frac{i_{D}}{v_{g s}}=\frac{i_{D 1}}{v_{g s}}=g_{m 1}$
To calculate $r_{o}$ :

\begin{aligned} v_{\pi 2} &=-I_{x} r_{01} \\ I_{x} &=g_{m 2} v_{\pi 2}+\frac{\left(V_{x}-I_{x} r_{01}\right)}{r_{02}} \\ I_{x} &=-g_{m 2} r_{01} I_{x}+\frac{V_{x}}{r_{02}}-I_{x} \frac{r_{01}}{r_{02}} \\ V_{x} &=r_{02}\left[1+r_{01} g_{m 2}+\frac{r_{01}}{r_{02}}\right] I_{x} \\ r_{0} &=\frac{V_{x}}{I_{x}}=r_{01}+r_{02}+r_{01} r_{02} g_{m 2} \\ & \approx r_{01} r_{02} g_{m 2} \end{aligned}
 Question 8
Assuming that transistors $M_{1}$ and $M_{2}$ are identical and have a threshold voltage of 1V, the state of transistors $M_{1}$ and $M_{2}$ are respectively.
 A Saturation, Saturation B Linear, Linear C Linear, Saturation D Saturation, Linear
GATE EC 2017-SET-2   Analog Circuits
Question 8 Explanation:

$\begin{array}{l} V_{G S 1}=2 V \\ V_{G S 2}=2.5-V_{x} \\ V_{D S 1}=V_{x} \\ V_{D S 2}=3-V_{x} \end{array}$
Assume both MOSFETs in saturation and equate their currents
\begin{aligned} I_{D S 1} &=I_{D S 2} \\ \frac{k_{n}}{2}(2-1)^{2} &=\frac{k_{n}}{2}\left(2.5-V_{x}-1\right)^{2} \end{aligned}
After solving, $V_{x}=0.5 \vee, 2.5 \mathrm{V}$
$V_{x}$ cannot be $2.5 \mathrm{V}$. Because this will make $M_{2}$ OFF.
Hence $V_{x}$ may be $0.5 \mathrm{V}$
$\Rightarrow M_{1}$ is in linear region.
$\Rightarrow M_{2}$ is in saturation region.
To verify further,
\begin{aligned} I_{D S 1} &=I_{D S 2} \\ k_{n}\left[(2-1) V_{n}-\frac{V_{x}^{2}}{2}\right]&=\frac{k_{n}}{2}\left(2.5-V_{x}-1\right)^{2} \end{aligned}
$V_{G S 2}=2.5 \mathrm{V}-V_{x}$ must be greater than $V_{T h}=1 V$
After solving, $V_{x}=0.588 \vee, 1.91 \mathrm{V}$
Hence correct value of $V_{x}=0.588 \mathrm{V}$
This varifies above conclusion i.e.
$M_{1} \rightarrow$ Linear region
$M_{2} \rightarrow$ Saturation region
 Question 9
An n-channel enhancement mode MOSFET is biased at $V_{GS}>V_{TH} \; and \; V_{DS}>(V_{GS}-V_{TH})$, where $V_{GS}$ is the gate-to-source voltage, $V_{DS}$ is the drain-to-source voltage and $V_{TH}$ is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves as a
 A voltage source with zero output impedance B voltage source with non-zero output impedance C current source with finite output impedance D current source with infinite output impedance
GATE EC 2017-SET-2   Analog Circuits
Question 9 Explanation:
The small signal equivalent circuit of MOSFET in saturation is as given below.

So, when the channel length modulation effect is significant, the MOSFET can be modelled as a current source with finite output impedance.
 Question 10
For the circuit shown, assume that the NMOS transistor is in saturation. Its threshold voltage $V _{tn}=1V$ and its transconductance parameter $\mu_{n}C_{OX}(\frac{W}{L})=1mA/V^{2}$ . Neglect channel length modulation and body bias effects. Under these conditions, the drain current $I_{D}$ in mA is ___________.
 A 4 B 1 C 2 D 3
GATE EC 2017-SET-1   Analog Circuits
Question 10 Explanation:
\begin{aligned} V_{G S}&=\frac{8 \times 5}{8}-1 \times I_{D}=5-I_{D} \\ &(\text{Here }I_{D}\text{ is numerically in mA }) \\ I_{D} &=5-V_{G S} \quad \ldots(i)\\ I_{D} &=\frac{\mu_{n} C_{o x}}{2} \frac{W}{L}\left(V_{G S}-V_{T}\right)^{2} \\ 5-V_{G S} &=\frac{1}{2}\left(V_{G S}-1\right)^{2} \\ 10-2 V_{G S} &=V_{G S}^{2}+1-2 V_{G S} \\ V_{G S}^{2} &=9 \Rightarrow V_{G S}=3 V \\ I_{D} &=5-3=2 \mathrm{mA} \end{aligned}
There are 10 questions to complete.