GATE EC 2017 SET-2

 Question 1
Consider the circuit shown in the figure.

The Boolean expression F implemented by the circuit is
 A $\bar{X}\bar{Y}\bar{Z}+XY+\bar{Y}Z$ B $\bar{X}Y \bar{Z}+XY+\bar{Y}Z$ C $\bar{X}Y \bar{Z}+XY+\bar{Y}Z$ D $\bar{X}\bar{Y}\bar{Z} +XY+\bar{Y}Z$
Digital Circuits   Combinational Circuits
Question 1 Explanation:

\begin{aligned} F_{1} &=\bar{X} Y \\ F &=\bar{Z} F_{1}+Z \bar{F}_{1} \\ &=(\bar{X} Y) \bar{Z}+(\bar{X} Y) Z \\ &=\bar{X} Y \bar{Z}+(X+\bar{Y}) Z \\ F &=\bar{X} Y \bar{Z}+X Z+\bar{Y} Z \end{aligned}
 Question 2
An LTI system with unit sample response h[n]=$5\delta [n]-7\delta [n-1]+7\delta [n-3]-5\delta [n-4]$ is a
 A Low - pass filter B high - pass filter C band - pass filter D band - stop filter
Signals and Systems   DTFS, DTFT and DFT
Question 2 Explanation:
\begin{aligned} h[n]=5 \delta[n]&-78[n-1]+7 \delta[n-3]-5 \delta[n-4] & \\ \text { Now, } \quad H\left(e^{j \omega}\right)&=5-7 e^{-j \omega}+7 e^{-3 j \omega}-5 e^{-4 j \omega}\\ \text{Now for }\omega & =0, \\ H\left(e^{j 0}\right)&=5-7+7-5=0\\ \text{and for }\omega & =\pi, &\\ H\left(e^{j \pi}\right) &=5-7(-1)+7(-1)-5(1) \\ &=5+7-7-5=0 \end{aligned}
System is attenuating low and high frequencies whereas passing the mid frequencies. So, its a BPF.

 Question 3
In the circuit shown, V is a sinusoidal voltage source. The current I is in phase with voltage V.
The ratio $\frac{amplitude \; of \; voltage \; across \; the \; capacitor} {amplitude \; of \; voltage \; across \; the \; resistor}$ is
 A 0.1 B 0.2 C 0.3 D 0.4
Network Theory   Sinusoidal Steady State Analysis
Question 3 Explanation:

Given that, V and J have same phase. So, the circuit is in resonance.
At resonance,
\begin{aligned} &V_{C}=Q V_{R}\\ &\text { So, } \frac{\text { Amplitude of } V_{C}}{\text { Amplitude of } V_{R}}=Q=\frac{1}{R} \sqrt{\frac{L}{C}}=\frac{1}{5} \sqrt{\frac{5}{5}}=0.2 \end{aligned}
 Question 4
In a DRAM,
 A periodic refreshing is not required B information is stored in a capacitor C information is stored in a latch D both read and write operations can be performed simultaneously
Digital Circuits   Memories
Question 4 Explanation:
In a DRAM, data is stored in the form of charge on capacitor and periodic refreshing is needed to restore the charge on capacitor.
 Question 5
Consider an n-channel MOSFET having width W, length L, electron mobility in the channel $\mu_{n}$ and oxide capacitance per unit area $C_{ox}$. If gate-to-source voltage $V_{GS}$=0.7V, drain-tosource voltage $V_{DS}=0.1V,(\mu_{n}C_{ox})=100\mu A/V^{2}$,threshold voltage $V_{TH}=0.3 V$ and (W/L)=50,then the transconductance $g_{m}$(in mA/V) is ___________.
 A 0.3 B 0.5 C 0.6 D 0.7
Electronic Devices   BJT and FET Basics
Question 5 Explanation:
Given that,
\begin{aligned} V_{G S} &=0.7 \mathrm{V}, V_{T H}=0.3 \mathrm{V}, V_{D S}=0.1 \mathrm{V} \\ V_{G S}-V_{T H} &=0.4>V_{D S} \end{aligned}
$\Rightarrow$ MOSFET is in linear region
In linear region,
$I_{D}=K_{n}\left[2\left(V_{G S}-V_{T H}\right) V_{O S}-V_{D S}^{2}\right]$
Transconductance
\begin{aligned} g_{m}&=\frac{\partial I_{D}}{\partial V_{G S}}=2 K_{n} V_{D S} \\ K_{n}&=\frac{K_{n}}{2}\left(\frac{W}{L}\right)=\frac{\mu_{n} C_{O x}}{2}\left(\frac{W}{L}\right)\\ \text{So,}\quad g_{m} &=2 K_{n} V_{D S}=\mu_{n} C_{O x}\left(\frac{W}{L}\right) V_{D S} \\ &=100 \times 50 \times 0.1 \mu \mathrm{A} / \mathrm{V} \\ &=0.5 \mathrm{mA} N \end{aligned}

There are 5 questions to complete.