GATE EC 2017 SET-2

Question 1
Consider the circuit shown in the figure.

The Boolean expression F implemented by the circuit is
A
\bar{X}\bar{Y}\bar{Z}+XY+\bar{Y}Z
B
\bar{X}Y \bar{Z}+XY+\bar{Y}Z
C
\bar{X}Y \bar{Z}+XY+\bar{Y}Z
D
\bar{X}\bar{Y}\bar{Z} +XY+\bar{Y}Z
Digital Circuits   Combinational Circuits
Question 1 Explanation: 


\begin{aligned} F_{1} &=\bar{X} Y \\ F &=\bar{Z} F_{1}+Z \bar{F}_{1} \\ &=(\bar{X} Y) \bar{Z}+(\bar{X} Y) Z \\ &=\bar{X} Y \bar{Z}+(X+\bar{Y}) Z \\ F &=\bar{X} Y \bar{Z}+X Z+\bar{Y} Z \end{aligned}
Question 2
An LTI system with unit sample response h[n]=5\delta [n]-7\delta [n-1]+7\delta [n-3]-5\delta [n-4] is a
A
Low - pass filter
B
high - pass filter
C
band - pass filter
D
band - stop filter
Signals and Systems   DTFS, DTFT and DFT
Question 2 Explanation: 
\begin{aligned} h[n]=5 \delta[n]&-78[n-1]+7 \delta[n-3]-5 \delta[n-4] & \\ \text { Now, } \quad H\left(e^{j \omega}\right)&=5-7 e^{-j \omega}+7 e^{-3 j \omega}-5 e^{-4 j \omega}\\ \text{Now for }\omega & =0, \\ H\left(e^{j 0}\right)&=5-7+7-5=0\\ \text{and for }\omega & =\pi, &\\ H\left(e^{j \pi}\right) &=5-7(-1)+7(-1)-5(1) \\ &=5+7-7-5=0 \end{aligned}
System is attenuating low and high frequencies whereas passing the mid frequencies. So, its a BPF.
Question 3
In the circuit shown, V is a sinusoidal voltage source. The current I is in phase with voltage V.
The ratio \frac{amplitude \; of \; voltage \; across \; the \; capacitor} {amplitude \; of \; voltage \; across \; the \; resistor} is
A
0.1
B
0.2
C
0.3
D
0.4
Network Theory   Sinusoidal Steady State Analysis
Question 3 Explanation: 


Given that, V and J have same phase. So, the circuit is in resonance.
At resonance,
\begin{aligned} &V_{C}=Q V_{R}\\ &\text { So, } \frac{\text { Amplitude of } V_{C}}{\text { Amplitude of } V_{R}}=Q=\frac{1}{R} \sqrt{\frac{L}{C}}=\frac{1}{5} \sqrt{\frac{5}{5}}=0.2 \end{aligned}
Question 4
In a DRAM,
A
periodic refreshing is not required
B
information is stored in a capacitor
C
information is stored in a latch
D
both read and write operations can be performed simultaneously
Digital Circuits   Memories
Question 4 Explanation: 
In a DRAM, data is stored in the form of charge on capacitor and periodic refreshing is needed to restore the charge on capacitor.
Question 5
Consider an n-channel MOSFET having width W, length L, electron mobility in the channel \mu_{n} and oxide capacitance per unit area C_{ox}. If gate-to-source voltage V_{GS}=0.7V, drain-tosource voltage V_{DS}=0.1V,(\mu_{n}C_{ox})=100\mu A/V^{2},threshold voltage V_{TH}=0.3 V and (W/L)=50,then the transconductance g_{m}(in mA/V) is ___________.
A
0.3
B
0.5
C
0.6
D
0.7
Electronic Devices   BJT and FET Basics
Question 5 Explanation: 
Given that,
\begin{aligned} V_{G S} &=0.7 \mathrm{V}, V_{T H}=0.3 \mathrm{V}, V_{D S}=0.1 \mathrm{V} \\ V_{G S}-V_{T H} &=0.4>V_{D S} \end{aligned}
\Rightarrow MOSFET is in linear region
In linear region,
I_{D}=K_{n}\left[2\left(V_{G S}-V_{T H}\right) V_{O S}-V_{D S}^{2}\right]
Transconductance
\begin{aligned} g_{m}&=\frac{\partial I_{D}}{\partial V_{G S}}=2 K_{n} V_{D S} \\ K_{n}&=\frac{K_{n}}{2}\left(\frac{W}{L}\right)=\frac{\mu_{n} C_{O x}}{2}\left(\frac{W}{L}\right)\\ \text{So,}\quad g_{m} &=2 K_{n} V_{D S}=\mu_{n} C_{O x}\left(\frac{W}{L}\right) V_{D S} \\ &=100 \times 50 \times 0.1 \mu \mathrm{A} / \mathrm{V} \\ &=0.5 \mathrm{mA} N \end{aligned}
Question 6
Two conducting spheres S1 and S2 of radii a and b (b>a) respectively, are placed far apart and connected by a long, thin conducting wire, as shown in the figure.

For some charge placed on this structure, the potential and surface electric field on S1 are V_{a} and E_{a}, and that on S2 are V_{b} and E_{b}, respectively, which of the following is CORRECT?
A
V_{a}=V_{b} \; and \; E_{a}\lt E_{b}
B
V_{a}\gt V_{b} \; and \; E_{a} \gt E_{b}
C
V_{a}=V_{b} \; and \; E_{a} \gt E_{b}
D
V_{a}\gt V_{b} \; and \; E_{a}=E_{b}
Electromagnetics   Basics of Electromagnetics
Question 6 Explanation: 


When charge is placed on this structure equilibrium is established such that be spheres are at same potential i.e.
V_{a}=V_{b}
\begin{array}{c} V_{a}=V_{b} \\ \text { So, } \frac{Q_{a}}{4 \pi \epsilon_{o} a}=\frac{Q_{b}}{4 \pi \epsilon_{o} b} \end{array}
\frac{Q_{b}}{Q_{a}}=\frac{b}{a}
Now, surface electric fields.
\frac{E_{a}}{E_{b}}=\left[\frac{Q_{a} / 4 \pi \varepsilon_{o} a^{2}}{Q_{b} / 4 \pi \varepsilon_{o} b^{2}}\right]=\frac{Q_{a} \times b^{2}}{Q_{b} \times a^{2}}=\frac{b}{a}>1
So, E_{a}>E_{b}
Question 7
For the circuit shown in the figure, P and Q are the inputs and Y is the output.

The logic implemented by the circuit is
A
XNOR
B
XOR
C
NOR
D
OR
Digital Circuits   Logic Families
Question 7 Explanation: 
As per GATE Answer key Marks to All.
Question 8
An n-channel enhancement mode MOSFET is biased at V_{GS}>V_{TH} \; and \; V_{DS}>(V_{GS}-V_{TH}), where V_{GS} is the gate-to-source voltage, V_{DS} is the drain-to-source voltage and V_{TH} is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves as a
A
voltage source with zero output impedance
B
voltage source with non-zero output impedance
C
current source with finite output impedance
D
current source with infinite output impedance
Analog Circuits   FET and MOSFET Analysis
Question 8 Explanation: 
The small signal equivalent circuit of MOSFET in saturation is as given below.


So, when the channel length modulation effect is significant, the MOSFET can be modelled as a current source with finite output impedance.
Question 9
A connection is made consisting of resistance A in series with a parallel combination of resistances B and C. Three resistors of value 10\Omega, 5\Omega, 2\Omega are provided. Consider all possible permutations of the given resistors into the positions A, B, C, and identify the configurations with maximum possible overall resistance, and also the ones with minimum possible overall resistance. The ratio of maximum to minimum values of the resistances (up to second decimal place) is ____________.
A
0.466
B
2.14
C
16.758
D
6.098
Network Theory   Basics of Network Analysis
Question 9 Explanation: 
The connection of resistors is as shown below:

Given resistor values are : 10 \Omega, 5 \Omega, 2 \Omega
The maximum resistance possible is,
\begin{aligned} R_{T(\max )} &=10 \Omega+(5 \Omega \| 2 \Omega) \\ &=\left(10+\frac{10}{7}\right) \Omega=\frac{80}{7} \Omega \end{aligned}
The minimum resistance possible is,
\begin{aligned} R_{T(\min )} &=2 \Omega+(10 \Omega \| 5 \Omega) \\ &=\left(2+\frac{10}{3}\right) \Omega=\frac{16}{3} \Omega \\ \frac{R_{T(\max )}}{R_{T(\min )}} &=\frac{80 / 7}{16 / 3}=\frac{15}{7}=2.143 \end{aligned}
Question 10
An npn bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base - collector junction is increased, then
A
the effective base width increases and common - emitter current gain increases
B
the effective base width increases and common - emitter current gain decreases
C
the effective base width decreases and common - emitter current gain increases
D
the effective base width decreases and common - emitter current gain decreases
Electronic Devices   BJT and FET Basics
Question 10 Explanation: 
When a BJT is in active region, as the reverse bias voltage across collector-base junction increased, the width of depletion region increases, which results in decrease of effective base width. This decrease in effective base width reduces the recombinations in base region, hence, common-emitter current gain will increase.
There are 10 questions to complete.
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