# IC Fabrication

 Question 1
The correct circuit representation of the structure shown in the figure is
 A A B B C C D D
GATE EC 2019   Electronic Devices
Question 1 Explanation:

 Question 2
There are two photolithography systems: one with light source of wavelength $\lambda _{1}$ = 156 nm (System 1) and another with light source of wavelength $\lambda _{2}$ = 325 nm (System 2). Both photolithography systems are otherwise identical. If the minimum feature sizes that can be realized using System1 and System2 are $L_{min1} \; and \; L_{min2}$ respectively, the ratio $L_{min1}/L_{min2}$(correct to two decimal places) is__________.
 A 0.5 B 1 C 1.5 D 0.25
GATE EC 2018   Electronic Devices
Question 2 Explanation:
\begin{aligned} L_{min}&\propto \lambda \\ \frac{L_{min1}}{L_{min2}}&=\frac{\lambda _1}{\lambda _2} \\ &= \frac{156nm}{325nm}=0.48 \end{aligned}
 Question 3
Which one of the following processes is preferred to form the gate dielectric ($SiO_{2}$) of MOSFETs ?
 A Sputtering B Molecular beam epitaxy C Wet oxidation D Dry oxidation
GATE EC 2015-SET-3   Electronic Devices
Question 3 Explanation:
Dry oxidation is preferred for gate oxides.
 Question 4
In MOSFET fabrication, the channel length is defined during the process of
 A isolation oxide growth B channel stop implantation C poly-silicon gate patterning D lithography step leading to the contact pads
GATE EC 2014-SET-3   Electronic Devices
Question 4 Explanation:
Channel length is defined during the poly-silicon gate pattering.
 Question 5
In CMOS technology, shallow P-well or N -well regions can be formed using
 A low pressure chemical vapour deposition B low energy sputtering C low temperature dry oxidation D low energy ion-implantation
GATE EC 2014-SET-2   Electronic Devices
Question 5 Explanation:
Ion implanation/diffusion is used for well implantation.
 Question 6
If fixed positive charges are present in the gate oxide of an n-channel enhancement type MOSFET, it will lead to
 A a decrease in the threshold voltage B channel length modulation C an increase in substrate leakage current D an increase in accumulation capacitance
GATE EC 2014-SET-1   Electronic Devices
Question 6 Explanation:
Fixed charges reduces threshold voltage.
 Question 7
In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapor) produces
 A superior quality oxide with a higher growth rate B inferior quality oxide with a higher growth rate C inferior quality oxide with a lower growth rate D superior quality oxide with a lower growth rate
GATE EC 2013   Electronic Devices
Question 7 Explanation:
Dry oxidation has better quality over wet oxidation.
Dry oxidation is slower over wet oxidation.
 Question 8
Thin gate oxide in a CMOS process in preferably grown using
 A wet oxidation B dry oxidation C epitaxial oxidation D ion implantation
GATE EC 2010   Electronic Devices
Question 8 Explanation:
Dry oxidation is prefferred for gate oxides.
 Question 9
A silicon wafer has 100 nm of oxide on it and is furnace at a temperature above $1000^{\circ}$ C for further oxidation in dry oxygen. The oxidation rate
 A is independent of current oxide thickness and temperature B is independent of current oxide thickness but depends on temperature C slows down as the oxide grows D is zero as the existing oxide prevents further oxidation
GATE EC 2008   Electronic Devices
Question 9 Explanation:
Growth rate
$\frac{d t o x}{d t}=\frac{B}{A+2 t o x}$
where A and B are oxidation constants.
as tox increases $\frac{d t o x}{d t}$ decreases.
 Question 10
If P is Passivation, Q is n -well implant, R is metallization and S is source/drain diffusion, then the order in which they are carried out in a standard n - well CMOS fabrication process, is
 A P - Q - R - S B Q - S - R - P C R - P - S - Q D S - R - Q - P
GATE EC 2003   Electronic Devices
Question 10 Explanation:

N Well CMOS fabrication process
Q : Well implant
S : Source/draimn diffusion
R : Metallisation
P : Passivation
There are 10 questions to complete.