Question 1 |
The correct circuit representation of the structure shown in the figure is


A | |
B | |
C | |
D |
Question 1 Explanation:

Question 2 |
There are two photolithography systems: one with light source of wavelength \lambda _{1} = 156 nm
(System 1) and another with light source of wavelength \lambda _{2} = 325 nm (System 2). Both
photolithography systems are otherwise identical. If the minimum feature sizes that can be
realized using System1 and System2 are L_{min1} \; and \; L_{min2} respectively, the ratio L_{min1}/L_{min2} (correct to two decimal places) is__________.
0.5 | |
1 | |
1.5 | |
0.25 |
Question 2 Explanation:
\begin{aligned} L_{min}&\propto \lambda \\ \frac{L_{min1}}{L_{min2}}&=\frac{\lambda _1}{\lambda _2} \\ &= \frac{156nm}{325nm}=0.48 \end{aligned}
Question 3 |
Which one of the following processes is preferred to form the gate dielectric (SiO_{2}) of MOSFETs ?
Sputtering | |
Molecular beam epitaxy | |
Wet oxidation | |
Dry oxidation |
Question 3 Explanation:
Dry oxidation is preferred for gate oxides.
Question 4 |
In MOSFET fabrication, the channel length is defined during the process of
isolation oxide growth | |
channel stop implantation | |
poly-silicon gate patterning | |
lithography step leading to the contact pads |
Question 4 Explanation:
Channel length is defined during the poly-silicon
gate pattering.
Question 5 |
In CMOS technology, shallow P-well or N -well regions can be formed using
low pressure chemical vapour deposition | |
low energy sputtering | |
low temperature dry oxidation | |
low energy ion-implantation |
Question 5 Explanation:
Ion implanation/diffusion is used for well
implantation.
Question 6 |
If fixed positive charges are present in the gate oxide of an n-channel
enhancement type MOSFET, it will lead to
a decrease in the threshold voltage | |
channel length modulation | |
an increase in substrate leakage current | |
an increase in accumulation capacitance |
Question 6 Explanation:
Fixed charges reduces threshold voltage.
Question 7 |
In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapor) produces
superior quality oxide with a higher growth rate | |
inferior quality oxide with a higher growth rate | |
inferior quality oxide with a lower growth rate | |
superior quality oxide with a lower growth rate |
Question 7 Explanation:
Dry oxidation has better quality over wet oxidation.
Dry oxidation is slower over wet oxidation.
Dry oxidation is slower over wet oxidation.
Question 8 |
Thin gate oxide in a CMOS process in preferably grown using
wet oxidation | |
dry oxidation | |
epitaxial oxidation | |
ion implantation |
Question 8 Explanation:
Dry oxidation is prefferred for gate oxides.
Question 9 |
A silicon wafer has 100 nm of oxide on it and is furnace at a temperature above 1000^{\circ} C for further oxidation in dry oxygen. The oxidation rate
is independent of current oxide thickness and temperature | |
is independent of current oxide thickness but depends on temperature | |
slows down as the oxide grows | |
is zero as the existing oxide prevents further oxidation |
Question 9 Explanation:
Growth rate
\frac{d t o x}{d t}=\frac{B}{A+2 t o x}
where A and B are oxidation constants.
as tox increases \frac{d t o x}{d t} decreases.
\frac{d t o x}{d t}=\frac{B}{A+2 t o x}
where A and B are oxidation constants.
as tox increases \frac{d t o x}{d t} decreases.
Question 10 |
If P is Passivation, Q is n -well implant, R is metallization and S is source/drain diffusion, then the order in which they are carried out in a standard n - well CMOS fabrication process, is
P - Q - R - S | |
Q - S - R - P | |
R - P - S - Q | |
S - R - Q - P |
Question 10 Explanation:

N Well CMOS fabrication process
Q : Well implant
S : Source/draimn diffusion
R : Metallisation
P : Passivation
There are 10 questions to complete.