IC Fabrication


Question 1
The correct circuit representation of the structure shown in the figure is
A
A
B
B
C
C
D
D
GATE EC 2019   Electronic Devices
Question 1 Explanation: 


Question 2
There are two photolithography systems: one with light source of wavelength \lambda _{1} = 156 nm (System 1) and another with light source of wavelength \lambda _{2} = 325 nm (System 2). Both photolithography systems are otherwise identical. If the minimum feature sizes that can be realized using System1 and System2 are L_{min1} \; and \; L_{min2} respectively, the ratio L_{min1}/L_{min2} (correct to two decimal places) is__________.
A
0.5
B
1
C
1.5
D
0.25
GATE EC 2018   Electronic Devices
Question 2 Explanation: 
\begin{aligned} L_{min}&\propto \lambda \\ \frac{L_{min1}}{L_{min2}}&=\frac{\lambda _1}{\lambda _2} \\ &= \frac{156nm}{325nm}=0.48 \end{aligned}


Question 3
Which one of the following processes is preferred to form the gate dielectric (SiO_{2}) of MOSFETs ?
A
Sputtering
B
Molecular beam epitaxy
C
Wet oxidation
D
Dry oxidation
GATE EC 2015-SET-3   Electronic Devices
Question 3 Explanation: 
Dry oxidation is preferred for gate oxides.
Question 4
In MOSFET fabrication, the channel length is defined during the process of
A
isolation oxide growth
B
channel stop implantation
C
poly-silicon gate patterning
D
lithography step leading to the contact pads
GATE EC 2014-SET-3   Electronic Devices
Question 4 Explanation: 
Channel length is defined during the poly-silicon gate pattering.
Question 5
In CMOS technology, shallow P-well or N -well regions can be formed using
A
low pressure chemical vapour deposition
B
low energy sputtering
C
low temperature dry oxidation
D
low energy ion-implantation
GATE EC 2014-SET-2   Electronic Devices
Question 5 Explanation: 
Ion implanation/diffusion is used for well implantation.


There are 5 questions to complete.