# Logic Families

 Question 1
Select the correct statement(s) regarding CMOS implementation of NOT gates.
 A Noise Margin High $(NM_H)$ is always equal to the Noise Margin Low $(NM_L)$ irrespective of the sizing of transistors. B Dynamic power consumption during switching is zero. C For a logical high input under steady state, the nMOSFET is in the linear regime of operation. D Mobility of electrons never influences the switching speed of the NOT gate.
GATE EC 2022   Digital Circuits
Question 1 Explanation:
(A) $NM_H$ will not be always equal to $NM_L$ because it depends on transistors parameters like size
$NM_H=V_{IL}-V_{OL}$
$NM_L=V_{OH}-V_{IH}$
Condition for $NM_H=NM_L$ : when $V_{TN}=|V_{TP}|\; and \; V_{IP}=\frac{V_{DD}}{2}$
If $\frac{K_p}{K_n}< > 1$ then $NM_H\neq NM_L$
(B) Due to capacitive leading of stage, dynamic power consumption during switching will not be zero.
(C) For $V_{DD}-|V_{TP}|\leq V_{in}\leq V_{DD}$ [logic high input]
PMOS $\rightarrow$ cut off
NMOS $\rightarrow$ Linear
(D) Mobility of electrons influences the switching speed because
Propagation delay,
$\tau _p=\frac{\tau _{PLH}+P_{PHL}}{2}$
$\tau _{PLH}=\frac{C_LV_{DD}}{\mu _p C_{ox} \frac{W}{L} (V_{GS}\;\; V_{TP})^2}$
$\mu _p$ dependent on mobality
Therefore (C) is only correct.
 Question 2
In the circuits shown, the threshold voltage of each Nmos transistor is 0.6 V. Ignoring the effect of channel length modulation and body bias, the values of Vout1 and Vout2, respectively, in volts, are
 A 1.8 and 1.2 B 2.4 and 2.4 C 1.8 and 2.4 D 2.4 and 1.2
GATE EC 2019   Digital Circuits
Question 2 Explanation:

$V_{\text {out } 1}=3-0.6-0.6=1.8 \mathrm{V}$

 Question 3
In the circuit shown, A and B are the inputs and Fis the output. What is the functionality of the circuit?
 A Latch B XNOR C SRAM Cell D XOR
GATE EC 2019   Digital Circuits
Question 3 Explanation:

So, the given logic circuit acts as an XNOR gate
 Question 4
In the circuit shown, what are the values of F for EN=0 and EN=1, respectively?
 A 0 and D B Hi-Z and D C 0 and 1 D Hi-Z and $\bar{D}$
GATE EC 2019   Digital Circuits
Question 4 Explanation:

When $E N=0$
$x_{1}=(\overline{D \cdot 0})=1 \Rightarrow$ PMOS is in OFF state
$x_{2}=(\overline{1+D})=0 \Rightarrow$ NMOS is in OFF state
Both the transistors are in OFF state, which offers high impedance.
\begin{aligned} \text { When } E N=1: x_{1}&=(\overline{D \cdot 1})=\bar{D} \\ x_{2}&=(\overline{0+D})=\bar{D} \\ F &=D \end{aligned}
 Question 5
A standard CMOS inverter is designed with equal rise and fall times ($\beta _n=\beta _p$). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin ($NM_L$) and the HIGH noise margin $NM_H$?
 A $NM_L$ increases and $NM_H$decreases B $NM_L$ decreases and $NM_H$ increases. C Both $NM_L$ and $NM_H$ increase. D No change in the noise margins.
GATE EC 2019   Digital Circuits
Question 5 Explanation:

Making PMOS wider, shifts input transition point $(V_{IT})$ towards $V_{DD}$
Making NMOS wider, shifts input transition point $(V_{IT})$ towards zero.
So, as PMOS made wider, NML increases and NMH decreases.

There are 5 questions to complete.