Logic Families

Question 1
In the circuits shown, the threshold voltage of each Nmos transistor is 0.6 V. Ignoring the effect of channel length modulation and body bias, the values of Vout1 and Vout2, respectively, in volts, are
A
1.8 and 1.2
B
2.4 and 2.4
C
1.8 and 2.4
D
2.4 and 1.2
GATE EC 2019   Digital Circuits
Question 1 Explanation: 


V_{\text {out } 1}=3-0.6-0.6=1.8 \mathrm{V}

Question 2
In the circuit shown, A and B are the inputs and Fis the output. What is the functionality of the circuit?
A
Latch
B
XNOR
C
SRAM Cell
D
XOR
GATE EC 2019   Digital Circuits
Question 2 Explanation: 




So, the given logic circuit acts as an XNOR gate
Question 3
In the circuit shown, what are the values of F for EN=0 and EN=1, respectively?
A
0 and D
B
Hi-Z and D
C
0 and 1
D
Hi-Z and \bar{D}
GATE EC 2019   Digital Circuits
Question 3 Explanation: 


When E N=0
x_{1}=(\overline{D \cdot 0})=1 \Rightarrow PMOS is in OFF state
x_{2}=(\overline{1+D})=0 \Rightarrow NMOS is in OFF state
Both the transistors are in OFF state, which offers high impedance.
\begin{aligned} \text { When } E N=1: x_{1}&=(\overline{D \cdot 1})=\bar{D} \\ x_{2}&=(\overline{0+D})=\bar{D} \\ F &=D \end{aligned}
Question 4
A standard CMOS inverter is designed with equal rise and fall times (\beta _n=\beta _p). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NM_L) and the HIGH noise margin NM_H?
A
NM_L increases and NM_Hdecreases
B
NM_L decreases and NM_H increases.
C
Both NM_L and NM_H increase.
D
No change in the noise margins.
GATE EC 2019   Digital Circuits
Question 4 Explanation: 


Making PMOS wider, shifts input transition point (V_{IT}) towards V_{DD}
Making NMOS wider, shifts input transition point (V_{IT}) towards zero.
So, as PMOS made wider, NML increases and NMH decreases.
Question 5
The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement "wired logic". Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.

The number of distinct values of X_{3}X_{2}X_{1}X_{0} (out of the 16 possible values) that give Y = 1 is _______.
A
5
B
6
C
8
D
7
GATE EC 2018   Digital Circuits
Question 5 Explanation: 


\begin{aligned} A&=\left(X_{1} \oplus X_{2}\right) \bar{X}_{3} \\ B&=\left[\left(X_{1} \oplus X_{2}\right) \bar{X}_{3} X_{0}\right] \cdot \bar{X}_{0}=0\\ Y&=B+X_{3}=0+X_{3}=X_{3} \end{aligned}
Out of 16 possible combinations of x_{3} x_{2} x_{1} x_{0} x_{3} , will be high for 8 combinations. So, Y will be high for 8 combinations.
Question 6
The logic function f(X,Y) realized by the given circuit is
A
NOR
B
AND
C
NAND
D
XOR
GATE EC 2018   Digital Circuits
Question 6 Explanation: 
From pull-down network,
\begin{aligned} \overline{f(X, Y)}&=\bar{X} \bar{Y}+X Y=X \odot Y \\ f(X, Y)&=\overline{X \odot Y}=X \oplus Y \end{aligned}
Question 7
For the circuit shown in the figure, P and Q are the inputs and Y is the output.

The logic implemented by the circuit is
A
XNOR
B
XOR
C
NOR
D
OR
GATE EC 2017-SET-2   Digital Circuits
Question 7 Explanation: 
As per GATE Answer key Marks to All.
Question 8
The logic functionality realized by the circuit shown below is
A
OR
B
XOR
C
NAND
D
AND
GATE EC 2016-SET-3   Digital Circuits
Question 8 Explanation: 
The output Y will be logic 1, when
A=1, B=1 and \bar{B}=0
\Rightarrow Y=A \cdot B \cdot \bar{B}=A \cdot B
\Rightarrow AND operation
Question 9
The functionality implemented by the circuit below is
A
2-to-1 multiplexer
B
4-to-1 multiplexer
C
7-to-1 multiplexer
D
6-to-1 multiplexer
GATE EC 2016-SET-1   Digital Circuits
Question 9 Explanation: 
When the outputs \left(O_{0^{\prime}} O_{1}, O_{2}, O_{3}\right) of the decoder are at logic 1, the corresponding tristate buffer is activated. In that case, whatever data is applied at the input of a buffer, becomes its output.
Hence, when
\begin{aligned} \Rightarrow \quad C_{1} C_{0}&=00, \quad \text{ Then } O_{0}=1, \\ \therefore \quad Y&=P \\ \Rightarrow \quad C_{1} C_{0}&=01, \quad \text{ Then } O_{1}=1 \\ \therefore \quad Y&=Q \\ \Rightarrow \quad C_{1} C_{0}&=10, \quad \text{ Then } O_{2}=1 \\ \therefore \quad Y&=R \\ \Rightarrow \quad C_{1} C_{0}&=11, \quad \text{ Then } O_{3}=1 \\ \therefore \quad Y&=S \end{aligned}
\therefore \quad the circuit effectively behaves as a 4 to 1 multiplexer.
Question 10
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing
A
NOR gates to NAND gates
B
inverters to buffers
C
NOR gates to NAND gates and inverters to buffers
D
5 V to ground
GATE EC 2015-SET-3   Digital Circuits
Question 10 Explanation: 
For TTL gate, open end acts as logic '1 '. So if we connect 5 V battery to ground then pressing the switches allow logic 'O' while opening the switches allow logic '1 '. In case of 5 V battery both opening and closing of switches allow logic '1' and hence circuit can't act as SR latch.
There are 10 questions to complete.
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