Question 1 |
Consider a Boolean gate (D) where the output Y is related to the inputs A and B as,
Y=A+\bar{B} , where + denotes logical OR operation. The Boolean inputs '0' and '1'
are also available separately. Using instances of only D gates and inputs '0' and '1',
__________ (select the correct option(s)).
NAND logic can be implemented | |
OR logic cannot be implemented | |
NOR logic can be implemented | |
AND logic cannot be implemented |
Question 1 Explanation:
\begin{aligned}
y &=A+\bar{B} =\overline{\bar{A}\cdot B}\\
f(A,B)&=A+\bar{B} \\
f(0,B) &=0+\bar{B}=\bar{B}\Rightarrow NOT\; Gate \\
f(A,\bar{B}) &=A+\bar{\bar{B}} =A+B\Rightarrow OR \;Gate\\
f(0,f(A,\bar{B}))&=0+(\overline{A+B})\Rightarrow NOR \; Gate \\
f(\bar{A},B) &= \bar{A}+\bar{B}=\overline{A\cdot B}\Rightarrow NAND\; Gate\\
f(0,f(\bar{A},B))&=0+\overline{\overline{A\cdot B}} =A\cdot B\Rightarrow AND \; Gate
\end{aligned}
Since, we can implement NOT Gate we can also implement OR, AND, NOR and NAND Gate.
Since, we can implement NOT Gate we can also implement OR, AND, NOR and NAND Gate.
Question 2 |
The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is
4 | |
5 | |
6 | |
7 |
Question 2 Explanation:
Question 3 |
The output of the combinational circuit given below is
A+B+C | |
A(B+C) | |
B(C+A) | |
C(A+B) |
Question 3 Explanation:
\begin{aligned} y &=A B C \oplus A B \oplus B C \\ &=[\overline{A B C} \cdot A B+A B C \cdot \overline{A B}] \oplus B C \\ &=[(\bar{A}+\bar{B}+\bar{C}) \cdot A B+A B C \cdot(\bar{A}+\bar{B})] \oplus B C \\ &=(A B \bar{C}) \oplus(B C) \\ &=\overline{A B \bar{C}} \cdot B C+A B \bar{C} \cdot \overline{B C} \\ &=(\bar{A}+\bar{B}+C) \cdot B C+A B \bar{C} \cdot(\vec{B}+\bar{C}) \\ &=\bar{A} B C+B C+A B \bar{C} \\ &=B C(\bar{A}+1)+A B \bar{C}=B C+A B \bar{C} \\ &=B(C+A \bar{C})=B(C+A) \end{aligned}
Question 4 |
A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE?
Gate 1 is a universal gate. | |
Gate 2 is a universal gate. | |
Gate 3 is a universal gate. | |
None of the gates shown is a universal gate |
Question 4 Explanation:
Universal gate is a gate by which every other gate
can be realized.
Gate 1 and Gate 2 are basic gates and can not be used as universal gates.
Gate 1 and Gate 2 are basic gates and can not be used as universal gates.
Question 5 |
In the figure shown, the output Y is required to be Y=AB+\bar{C}\bar{D}.The gates G1 and G2 must be, respectively,
NOR, OR | |
OR, NAND | |
NAND, OR | |
AND, NAND |
Question 5 Explanation:
\begin{aligned} Y &=A B+\bar{C} \bar{D} \\ G_1 &=\text { NOR Gate } \quad \bar{A} \text{ NOR } \bar{B}=A B \\ G 2 &=\text { OR GATE } \quad A B+\bar{C} \bar{D} \end{aligned}
Question 6 |
A 3-input majority gate is defined by the logic function M(a,b,c) = ab + bc + ca . Which one of the following gates is represented by the function M(M\overline{(a,b,c)},M(a,b,\bar{c}),c) ?
3-input NAND gate | |
3-input XOR gate | |
3-input NOR gate | |
3-input XNOR gate |
Question 6 Explanation:
\begin{aligned} M(a, b, c) &=a b+b c+c a \\ \overline{M(a, b, c)} &=\frac{a b+b c+c a}{a b \cdot b c} \cdot \overline{c a} \\ &=(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a}) \\ M(a, b, \bar{c}) &=a b+b \bar{c}+\bar{c} a \end{aligned}
\begin{array}{l} \begin{aligned} M(\overline{M(a, b, c)}, M(a, b, \bar{c}) c) &=\\ \left[\begin{array}{l}(\overline{a b} \cdot \overline{b c} \cdot \overline{c a})(a b+b \bar{c}+\overline{c a}) \\ +(a b+b \bar{c}+\bar{c} a)(c)+(\overline{a b} \cdot \overline{b c} \cdot \bar{a} a \mid)\end{array}\right]\end{aligned} \\ =\left[\begin{array}{l} (\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})(a b+b \bar{c}+\bar{c} a) \\ +a b c+(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a}) c \end{array}\right] \\ =(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})[a b+b \bar{c}+\bar{c} a+c]+a b c \\ =(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})[a+b+c]+a b c \\ =(\bar{a} \bar{b}+\bar{b} \bar{c}+\bar{c} \bar{a})[a+b+c]+a b c \\ F=a \bar{b} \bar{c}+b \bar{c} \bar{a}+c \bar{a} \bar{b}+a b c \\ F=A \oplus B \oplus C \end{array}
\begin{array}{l} \begin{aligned} M(\overline{M(a, b, c)}, M(a, b, \bar{c}) c) &=\\ \left[\begin{array}{l}(\overline{a b} \cdot \overline{b c} \cdot \overline{c a})(a b+b \bar{c}+\overline{c a}) \\ +(a b+b \bar{c}+\bar{c} a)(c)+(\overline{a b} \cdot \overline{b c} \cdot \bar{a} a \mid)\end{array}\right]\end{aligned} \\ =\left[\begin{array}{l} (\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})(a b+b \bar{c}+\bar{c} a) \\ +a b c+(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a}) c \end{array}\right] \\ =(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})[a b+b \bar{c}+\bar{c} a+c]+a b c \\ =(\bar{a}+\bar{b})(\bar{b}+\bar{c})(\bar{c}+\bar{a})[a+b+c]+a b c \\ =(\bar{a} \bar{b}+\bar{b} \bar{c}+\bar{c} \bar{a})[a+b+c]+a b c \\ F=a \bar{b} \bar{c}+b \bar{c} \bar{a}+c \bar{a} \bar{b}+a b c \\ F=A \oplus B \oplus C \end{array}
Question 7 |
All the logic gates shown in the figure have a propagation delay of 20 ns. Let A = C = 0 and B = 1 until time t = 0. At t = 0, all the inputs flip (i.e., A = C = 1 and B = 0) and remain in that state. For t > 0, output Z = 1 for a duration (in ns) of ______________.
20 | |
30 | |
40 | |
50 |
Question 7 Explanation:
Z is '1' for 40 n-sec.
Question 8 |
In the circuit shown in the figure, if C = 0, the expression for Y is
Y=A\bar{B}+\bar{A}B | |
Y=A+B | |
Y=\bar{A}+\bar{B} | |
Y=AB |
Question 8 Explanation:
Output of gate 1: \bar{C}
Output of gate 2: \rightarrow(\overline{A+B})
Output of gate 3: \rightarrow(\overline{A+B}+C)
Output of gate 4: \rightarrow AB
Output of gate 5: \rightarrow(\overline{A+B}+C)+A B
Output of gate 6 is output Y i.e.
\begin{aligned} Y &=\overline{\bar{C} \cdot(\overline{A+B}+C)+A B} \\ &=C+\overline{(\overline{A+B}+C+A B)} \end{aligned}
Using Demorgan's theorem
\begin{aligned} &=C+(\overline{\overline{A+B}}) \cdot \bar{C} \cdot(\overline{A B})\\ &=C+(A+B) \cdot \bar{C} \cdot(\bar{A}+\bar{B}) \end{aligned}
Given in question C=0
\begin{aligned} \text{So, }Y&=0+(A+B) \cdot \overline{0} \cdot(\bar{A}+\bar{B}) \\ &=\bar{A} B+A \bar{B} \end{aligned}
Question 9 |
The output F in the digital logic circuit shown in the figure is
F=\bar{X}YZ+X\bar{Y}Z | |
F=\bar{X}Y\bar{Z}+X\bar{Y}\bar{Z} | |
F=\bar{X}\bar{Y}Z+XYZ | |
F=\bar{X}\bar{Y}\bar{Z}+XYZ |
Question 9 Explanation:
\begin{aligned} A &=X \oplus Y \\ B &=A \odot Z=A \cdot Z+\bar{A} \bar{Z} \\ &=Z(X \oplus Y)+(X \odot Y) \bar{Z} \\ F &=A B \\ &=(X \oplus Y)[Z(X \oplus Y)+\bar{Z}(\overline{X \oplus Y})] \\ &=Z[(X \oplus Y)(X \oplus Y)+\bar{A}(\overline{X \oplus Y})(X \oplus Y)] \\ &\begin{aligned} \text { as we know } A \cdot A &=A \\ A \cdot \bar{A} &=0 \\ &=Z[(X \oplus Y)+0] \\ &=\bar{X} Y Z+X \bar{Y} Z \end{aligned} \end{aligned}
Question 10 |
A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles
an AND gate | |
an OR gate | |
an XOR gate | |
a NAND gate |
Question 10 Explanation:
Truth table of XOR gate
\begin{array}{cc|c} A & B & Y \\ \hline 0 & 0 & 0 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \end{array}
So, from the XOR gate truth table it is clear that the bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch.
\begin{array}{cc|c} A & B & Y \\ \hline 0 & 0 & 0 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \end{array}
So, from the XOR gate truth table it is clear that the bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch.
There are 10 questions to complete.