Question 1 |

Addressing of a 32K\:\times\:16 memory is realized using a single decoder. The minimum number of \text{AND} gates required for the decoder is

2^{8} | |

2^{32} | |

2^{15} | |

2^{19} |

Question 1 Explanation:

For N \times 2^{N}, decoder, there are 2^{N} AND gates required at output

\therefore 32 \mathrm{~K} \times 16=2^{5} \times 2^{10} \times 16=2^{15} \times 16

\therefore 2^{15} AND gates required to realize the given memory address

\therefore 32 \mathrm{~K} \times 16=2^{5} \times 2^{10} \times 16=2^{15} \times 16

\therefore 2^{15} AND gates required to realize the given memory address

Question 2 |

A 2\times 2 ROM array is built with the help of diodes as shown in the circuit below. Here W0
and W1 are signals that select the word lines and B0 and B1 are signals that are output of the
sense amps based on the stored data corresponding to the bit lines during the read operation.

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to D_{ij} (where i = 0 or 1 and j = 0 or 1) stored in the ROM?

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to D_{ij} (where i = 0 or 1 and j = 0 or 1) stored in the ROM?

\begin{bmatrix} 1 & 0\\ 0 & 1 \end{bmatrix} | |

\begin{bmatrix} 0 & 1\\ 1 & 0 \end{bmatrix} | |

\begin{bmatrix} 1 & 0\\ 1 & 0 \end{bmatrix} | |

\begin{bmatrix} 1 & 1\\ 0 & 0 \end{bmatrix} |

Question 2 Explanation:

\begin{array}{l} \text { When, } W_{0}=V_{D O}, B_{0}=V_{D D} \text { ; otherwise } B_{0}=0 \\ \text { When } W_{1}=V_{D O} B_{1}=V_{D D} \text { ; otherwise } B_{1}=0 \\ \text { So, } B_{0}=W_{0} \text { and } B_{1}=W_{1} \\ \text { Hence } \begin{array}{c|cc} &B_{0}&B_{1}\\ \hline W_{0}&1&0\\ W_{1}&0&1 \end{array}\\ \end{array}

Question 3 |

In a DRAM,

periodic refreshing is not required | |

information is stored in a capacitor | |

information is stored in a latch | |

both read and write operations can be performed simultaneously |

Question 3 Explanation:

In a DRAM, data is stored in the form of charge
on capacitor and periodic refreshing is needed to
restore the charge on capacitor.

Question 4 |

If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in

A | |

B | |

C | |

D |

Question 4 Explanation:

Question 5 |

In the circuit shown in the figure, A is parallel-in, parallel-out 4 bit register, which loads at the rising edge of the clock C . The input lines are connected to a 4 bit bus, W. Its output acts at input to a 16\times4 ROM whose output is floating when the enable input E is 0. A partial table of the contents of the ROM is as follows

The clock to the register is shown, and the data on the W bus at time t_{1} is 0110. The data on the bus at time t_{2} is

The clock to the register is shown, and the data on the W bus at time t_{1} is 0110. The data on the bus at time t_{2} is

1111 | |

1011 | |

1000 | |

0010 |

Question 5 Explanation:

When W has data 0110 i.e. 6 in decimal its data
value at that add. is 1010.

Now 1010 i.e. 10 is acting as add. at time t_{2} and data at that moment is 1000.

Now 1010 i.e. 10 is acting as add. at time t_{2} and data at that moment is 1000.

Question 6 |

If the input X_3, X_2, X_1, X_0 to the ROM in figure are 8-4-2-1 BCD numbers,
then the outputs Y_3Y_2Y_1Y_0 are

gray code numbers | |

2-4-2-1 BCD numbers | |

excess 3 code numbers | |

none of the above |

Question 6 Explanation:

\begin{array}{ccccccccc} &&&&4&3&2&1&\\ x_{3} & x_{2} & x_{1} & x_{0} & y_{3} & y_{2} & y_{1} & y_{0} & \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & \rightarrow 0 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & \rightarrow 1 \\ 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & \rightarrow 2 \\ 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 & \rightarrow 3 \\ 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & \rightarrow 4 \\ 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & \rightarrow 5 \\ 0 & 1 & 1 & 0 & 1 & 1 & 0 & 0 & \rightarrow 6 \\ 0 & 1 & 1 & 1 & 1 & 1 & 0 & 1 & \rightarrow 7 \\ 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & \rightarrow 8 \\ 1 & 0 & 0 & 1 & 1 & 1 & 1 & 1 & \rightarrow 9 \end{array}

\therefore \text{ is }8421BCD\text{ to }2421BCD

\therefore \text{ is }8421BCD\text{ to }2421BCD

Question 7 |

In the DRAM cell in figure, the V_{t} of the NMOSFET is 1 V. For the following three combinations of WL and BL voltages.

5 V; 3V; 7V | |

4 V; 3V; 4V | |

5 V; 5V; 5V | |

4 V; 4V; 4V |

There are 7 questions to complete.