Microprocessors

\begin{aligned}2^{n}&=N \\ n & \rightarrow \text{ Number of Address Lines} \\ N & \rightarrow \text{ Number of Memory Locations} \\ 2^{n}&=16 KB \\ &=2^{4} (2^{10}) \\ &=2^{14}\\ n&=14\end{aligned}

\begin{aligned} \text { MVI } A, 33 H &: (A)=33 H \\ \text { MVI B, } 78 \text { H } &: \text { (B) }=78 \mathrm{H} \\ \text { ADD } \mathrm{B} &: (\mathrm{A}) \leftarrow(\mathrm{A})+(\mathrm{B})=33 \mathrm{H} \\ +78 \mathrm{H}=\mathrm{AB} &\text { H } \Rightarrow (\mathrm{A})=\mathrm{AB} \mathrm{H} \\ &\text { (A) }=10101011\\ CMA&:\text{Complement}\\ \text { Accumulator } &\Rightarrow(A) =01010100 \\ \text { ANI } 32 \mathrm{H} &:\text { (A) } \leftarrow(\text { A) AND } 32 \mathrm{H} \\ &\quad 01010100\\ &\quad 00110010\\ &\quad 10010000 \Rightarrow(A)=10 H \end{aligned}

Given than,
f_{\mathrm{CLK}}=5 \mathrm{MHz}
Execution time =1.4 \mu \mathrm{s}
Execution time =n(T-\text { state })
n= number of T-states required to execute the instruction
T- state (or) T_{\mathrm{CLK}}=\frac{1}{f_{\mathrm{CLK}}}=0.2 \mu \mathrm{s}
So, \quad n=\frac{1.4 \mu \mathrm{s}}{T_{\mathrm{CLK}}}=\frac{1.4}{0.2}=7

RLC: Rotate accumulator left by 1 bit without carry


Before RLC operation:
\begin{aligned} A &=A 7 H=(10100111)_{2} \\ C Y &=0 \end{aligned}
After RLC operation:
\begin{aligned} A &=(01001111)_{2}=4 \mathrm{FH} \\ \mathrm{CY} &=1 \end{aligned}

\begin{aligned} & \text {8kB ROM is given }\\ &\therefore 2^{n}=8 k B=2^{3}\left(2^{10}\right)=2^{13} \end{aligned}


\therefore 13 Address lines are required for memory chip.
But the address range given as 1000H-2FFF H


In order to get \overline{C S} as low, the condition is
A_{15}=A_{14}=0 and A_{13}=0 / 1, A_{12}=1 / 0
The circuit to generate an active low chip select signal can be given as shown below:


The logical expression can be written as,
\begin{aligned} F &=A_{15}+A_{14}+\left(A_{13} \odot A_{12}\right) \\ &=A_{15}+A_{14}+\left(A_{13} \cdot A_{12}+\bar{A}_{13} \cdot \bar{A}_{12}\right) \end{aligned}

The stack pointer needs to be pre-decremented before wiriting data into stack. For reading data from stack, such pre-decrement or pre-increment operations are not needed, as already stack pointer indicates the address of stack top from where the read operation takes place. Hence, PUSH operation requires more clock cycles than POP operation.

Product can be obtained by repeated addition.
Only {C) option satisfied addition repeatedly.
Here register 'B' is used as count to add register 'C' to accumulator, initially having OOH. Adding 'B' times 'C' to accumulator.

The only instruction that changes the contents of accumulator is SBI BEH.

Memory size =16 \mathrm{kB}=214 \mathrm{bits }
Number of address lines = Number of data lines
\begin{aligned} 2^{n} \cdot 2^{n} &=2^{14} \\ \quad n &=7 \end{aligned}

Shift register are accumulator and flag register
(A and F).