# Microprocessors

 Question 1
In an 8085 microprocessor, the number of address lines required to access a 16 K byte memory bank is __________.
 A 16 B 14 C 12 D 15
GATE EC 2020      Basics of 8085 Microprocessor
Question 1 Explanation:
\begin{aligned}2^{n}&=N \\ n & \rightarrow \text{ Number of Address Lines} \\ N & \rightarrow \text{ Number of Memory Locations} \\ 2^{n}&=16 KB \\ &=2^{4} (2^{10}) \\ &=2^{14}\\ n&=14\end{aligned}
 Question 2
The following FIVE instructions were executed on an 8085 microprocessor.
MVI A, 33H
MVI B, 78H
CMA
ANI 32H
The Accumulator value immediately after the execution of the fifth instruction is
 A 00H B 10H C 11H D 32H
GATE EC 2017-SET-1      Microprocessor 8085 Programming
Question 2 Explanation:
\begin{aligned} \text { MVI } A, 33 H &: (A)=33 H \\ \text { MVI B, } 78 \text { H } &: \text { (B) }=78 \mathrm{H} \\ \text { ADD } \mathrm{B} &: (\mathrm{A}) \leftarrow(\mathrm{A})+(\mathrm{B})=33 \mathrm{H} \\ +78 \mathrm{H}=\mathrm{AB} &\text { H } \Rightarrow (\mathrm{A})=\mathrm{AB} \mathrm{H} \\ &\text { (A) }=10101011\\ CMA&:\text{Complement}\\ \text { Accumulator } &\Rightarrow(A) =01010100 \\ \text { ANI } 32 \mathrm{H} &:\text { (A) } \leftarrow(\text { A) AND } 32 \mathrm{H} \\ &\quad 01010100\\ &\quad 00110010\\ &\quad 10010000 \Rightarrow(A)=10 H \end{aligned}
 Question 3
The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 $\mu s$, then the number of T-states needed for executing the instruction is
 A 1 B 6 C 7 D 8
GATE EC 2017-SET-1      Instructions of 8085 Microprocessor
Question 3 Explanation:
Given than,
$f_{\mathrm{CLK}}=5 \mathrm{MHz}$
Execution time $=1.4 \mu \mathrm{s}$
Execution time $=n(T-\text { state })$
$n=$ number of T-states required to execute the instruction
T- state (or) $T_{\mathrm{CLK}}=\frac{1}{f_{\mathrm{CLK}}}=0.2 \mu \mathrm{s}$
So, $\quad n=\frac{1.4 \mu \mathrm{s}}{T_{\mathrm{CLK}}}=\frac{1.4}{0.2}=7$
 Question 4
In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in hex) and 0, respectively. If the instruction RLC is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be
 A 4E and 0 B 4E and 1 C 4F and 0 D 4F and 1
GATE EC 2016-SET-3      Instructions of 8085 Microprocessor
Question 4 Explanation:
RLC: Rotate accumulator left by 1 bit without carry

Before RLC operation:
\begin{aligned} A &=A 7 H=(10100111)_{2} \\ C Y &=0 \end{aligned}
After RLC operation:
\begin{aligned} A &=(01001111)_{2}=4 \mathrm{FH} \\ \mathrm{CY} &=1 \end{aligned}
 Question 5
An 8 Kbyte ROM with an active low Chip Select input ($\overline{CS}$) is to be used in an 8085 microprocessor based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as $A_{15} \; to \; A_{0}, \; where \; A_{15}$ is the most significant address bit. Which one of the following logic expressions will generate the correct $\overline{CS}$ signal for this ROM?
 A $A_{15} + A_{14} + (A_{13}\cdot A_{12}+ \bar{A_{13}}\cdot \bar{A_{12}})$ B $A_{15} \cdot A_{14} \cdot (A_{13}+ A_{12})$ C $\bar{A_{15}} \cdot \bar{A_{14}} \cdot (A_{13}\cdot \bar{A_{12}}+ \bar{A_{13}}\cdot A_{12})$ D $\bar{A_{15}} + \bar{ A_{14}} +A_{13}\cdot A_{12}$
GATE EC 2016-SET-2      Interfacing and Peripheral Devices
Question 5 Explanation:
\begin{aligned} & \text {8kB ROM is given }\\ &\therefore 2^{n}=8 k B=2^{3}\left(2^{10}\right)=2^{13} \end{aligned}

$\therefore$ 13 Address lines are required for memory chip.
But the address range given as 1000H-2FFF H

In order to get $\overline{C S}$ as low, the condition is
$A_{15}=A_{14}=0$ and $A_{13}=0 / 1, A_{12}=1 / 0$
The circuit to generate an active low chip select signal can be given as shown below:

The logical expression can be written as,
\begin{aligned} F &=A_{15}+A_{14}+\left(A_{13} \odot A_{12}\right) \\ &=A_{15}+A_{14}+\left(A_{13} \cdot A_{12}+\bar{A}_{13} \cdot \bar{A}_{12}\right) \end{aligned}
 Question 6
In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?
 A For POP, the data transceivers remain in the same direction as for instruction fetch (memory to processor), whereas for PUSH their direction B174has to be reversed. B Memory write operations are slower than memory read operations in an 8085 based system. C The stack pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP operation uses the address already in the stack pointer. D Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.
GATE EC 2016-SET-1      Instructions of 8085 Microprocessor
Question 6 Explanation:
The stack pointer needs to be pre-decremented before wiriting data into stack. For reading data from stack, such pre-decrement or pre-increment operations are not needed, as already stack pointer indicates the address of stack top from where the read operation takes place. Hence, PUSH operation requires more clock cycles than POP operation.
 Question 7
Which one of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C?
 A MVI A, 00H JNZ LOOP CMP C LOOP: DCR B HLT B MVI A, 00H CMP C LOOP: DCR B JNZ LOOP HLT C MVI A, 00H LOOP: ADD C DCR B JNZ LOOP HLT D MVI A, 00H ADD C JNZ LOOP LOOP: INR B HLT
GATE EC 2015-SET-3      Microprocessor 8085 Programming
Question 7 Explanation:
Product can be obtained by repeated addition.
Only {C) option satisfied addition repeatedly.
Here register 'B' is used as count to add register 'C' to accumulator, initially having OOH. Adding 'B' times 'C' to accumulator.
 Question 8
In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?
 A MOV B,M B PCHL C RNZ D SBI BEH
GATE EC 2015-SET-2      Instructions of 8085 Microprocessor
Question 8 Explanation:
The only instruction that changes the contents of accumulator is SBI BEH.
 Question 9
A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is _______.
 A 6 B 7 C 8 D 9
GATE EC 2015-SET-1      Interfacing and Peripheral Devices
Question 9 Explanation:
Memory size $=16 \mathrm{kB}=214 \mathrm{bits }$
Number of address lines = Number of data lines
\begin{aligned} 2^{n} \cdot 2^{n} &=2^{14} \\ \quad n &=7 \end{aligned}
 Question 10
In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively
 A B and F B A and F C H and F D A and C
GATE EC 2015-SET-1      Basics of 8085 Microprocessor
Question 10 Explanation:
Shift register are accumulator and flag register
(A and F).
There are 10 questions to complete.