Operational Amplifiers

Question 1
The components in the circuit given below are ideal. If R = 2 k\Omega and C = 1 \mu F, the -3 dB cut-off frequency of the circuit in Hz is
A
14.92
B
34.46
C
59.68
D
79.58
GATE EC 2020   Analog Circuits
Question 1 Explanation: 
Op-amp active filter (LPF) inverting type 3 dB cut-off frequency,
f_{c}=\frac{1}{2\pi RC}=\frac{1}{2\pi \times 2\times 10^{3}\times 10^{-6}}=\frac{500}{2\pi }=79.58Hz
Question 2
In the circuit shown below, all the components are ideal. If V_i is +2 V, the current I_o sourced by the op-amp is __________ mA.
A
4
B
6
C
2
D
1
GATE EC 2020   Analog Circuits
Question 2 Explanation: 
\begin{aligned} V_o=(1+1) \times 2&=4V \\ \text{KCL at node } V_o & \\ \frac{2-4}{1k\Omega }I_o+\frac{0-4}{1k\Omega }&=0 \\ -2+I_o-4 &=0 \\ I_o&=6mA \end{aligned}
Question 3
The components in the circuit shown below are ideal. If the op-amp is in positive feedback and the input voltage V_i is a sine wave of amplitude 1 V, the output voltage V_o is
A
a non-inverted sine wave of 2 V amplitude
B
an inverted sine wave of 1 V amplitude
C
a square wave of 5 V amplitude
D
a constant of either +5 or -5V
GATE EC 2020   Analog Circuits
Question 3 Explanation: 


Given circuit is a Schmitt trigger of non-inverting type.
V_{o}=\pm 5\, V
V^{+}=\frac{V_{o}\times 1+V_{i}\times 1}{1+1}=\frac{V_{o}+V}{2}
let, V_{o}=-5\, V,\, \, \, \,V^{+}=\frac{-5+V_{i}}{2}
V_{o} can change from -5 V to +5 V if V^{+} \gt 0
i.e. \frac{-5+V_{i}}{2} \gt 0\Rightarrow V_{i} \gt 5\, V
similarly, V_{o} can change from -5 V to +5 V if V_{i} \lt -5\, V
But given input has peak value 1 V. Hence output cannot change from +5 V to -5 V or -5 V to +5 V.
Output remain constant at +5 V or -5 V.
Question 4
An op-amp based circuit is implemented as shown below.

In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to one decimal place) at node A, connected to the negative input of the op-amp as indicated in the figure is _________.
A
0.4
B
0.8
C
0.3
D
1
GATE EC 2018   Analog Circuits
Question 4 Explanation: 
Applying the concept of virtual ground, we get
\begin{aligned} V_{o}&=-\frac{R_{2}}{R_{1}} \cdot V_{i n}\\ [\therefore & \text{ non-inverting amplifiel}]\\ \therefore \quad V_{o}&=-\frac{31 \mathrm{k} \Omega}{1 \mathrm{k} \Omega} \times 1 \mathrm{V}\\ V_{0}&=-31 \mathrm{V} \lt -15 \mathrm{V} \end{aligned}
which is not possible
Hence, the output voltage of the op-amp is equal to -15 \mathrm{V}


Now applying KCL of node 'A', we get.
\begin{aligned} \frac{V_{A}-(-15)}{31 \mathrm{k} \Omega}+\frac{V_{A}-1}{1 \mathrm{k} \Omega} &=0 \\ \frac{V_{A}}{31 \mathrm{k} \Omega}+\frac{V_{A}}{1 \mathrm{k} \Omega} &=\frac{-15}{31 \mathrm{k} \Omega}+\frac{1}{1 \mathrm{k} \Omega} \\ V_{A}\left[\frac{1}{31}+\frac{1}{1}\right] &=-\frac{15}{31}+1 \\ V_{A} &=0.5 \mathrm{V} \end{aligned}
Question 5
In the circuit shown below, the op-amp is ideal and Zener voltage of the diode is 2.5 volts. At the input, unit step voltage is applied, i.e. v_{IN}(t)= u(t) volts. Also, at t= 0, the voltage across each of the capacitors is zero.
The time t, in milliseconds, at which the output voltage v_{OUT} crosses -10 V is
A
2.5
B
5
C
7.5
D
10
GATE EC 2018   Analog Circuits
Question 5 Explanation: 
\text{For} \quad t \gt 0,


I=\frac{1 V}{1 \mathrm{k} \Omega}=1 \mathrm{mA}
Till t=2.5 \mathrm{msec}, both V_{1} and V_{2} will increase and after t=2.5 \mathrm{msec}, V_{2}=2.5 \mathrm{V} and V_{1} increases with time.
\begin{aligned} \text { when } v_{\text {out }}(t) &=-10 \mathrm{V} \\ & V_{1}=7.5 \mathrm{V}\\ \text{So,}\\ \frac{1}{1 \mu F} \int_{0}^{t}(1 \mathrm{m} \mathrm{A}) d t &=7.5 \mathrm{V} \\ 10^{3} t &=7.5 \\ t &=7.5 \mathrm{msec} \end{aligned}
Question 6
In the voltage reference circuit shown in the figure, the op-amp is ideal and the transistors Q_{1},Q_{2}...,Q_{32} are identical in all respects and have infinitely large values of common-emitter current the relation I_{C}=I_{S}\; exp \;(V_{BE}/V_{T}), where I_{s} is the saturation current. Assume that the voltage V_{P} shown in the figure is 0.7 V and the thermal voltage V_{T} =26mV. The output voltage V_{out} (in volts) is__________.
A
0.65
B
1.14
C
1.68
D
1.82
GATE EC 2017-SET-2   Analog Circuits
Question 6 Explanation: 


KCL at a
\begin{aligned} \frac{V_{0}-V_{x}}{20} &=\frac{V_{x}-0.7}{5} \\ V_{0}-V_{x} &=4 V_{x}-2.8 \\ V_{0} &=5 V_{x}-2.8 \quad\ldots(i)\\ \text{Now,}\quad I_{1} &=31 I \\ I_{s} e^{V_{x} / V_{I}} &=31 I_{s} e^{v_{p} / v_{T}} \\ \frac{V_{x}}{V_{T}} &=\ln 31+\frac{V_{P}}{V_{T}} \\ \frac{V_{x}-V_{P}}{V_{T}} &=\ln 31 \\ \Rightarrow\qquad V_{x} &=0.789 \mathrm{V} \end{aligned}
rom equation (i)
V_{0}=5 \times 0.789-2.8=1.145 \mathrm{V}
Question 7
The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-amp), and has an open-loop voltage gain, A_{o}=10^{5}V/V and an open-loop cut-off frequency f_{c}=8Hz. The voltage gain of the amplifier at 15 kHz, in V/V is __________.
A
37.5
B
44.4
C
50.2
D
55.6
GATE EC 2017-SET-1   Analog Circuits
Question 7 Explanation: 
In the given circuit,
Feedback factor, \beta=\frac{R_{1}}{R_{1}+R_{2}}=\frac{1}{80}


A_{o f}=\frac{A_{o}}{1+A_{o} \beta} \simeq 80
f_{c}^{\prime}=f_{c}\left(1+A_{o} \beta\right)=8\left(1+\frac{10^{5}}{80}\right) \mathrm{Hz}=10,008 \mathrm{Hz}
Gain at f=15 \mathrm{kHz}=15000 \mathrm{Hz} is,
A_{f}=\frac{A_{\mathrm{b}}}{\sqrt{1+\left(\frac{f}{f_{c}^{2}}\right)^{2}}}=\frac{80}{\sqrt{\left(1+\left(\frac{15000}{10008}\right)^{2}\right)}} \simeq 44.4
Question 8
For the operational amplifier circuit shown, the output saturation voltages are \pm15V. The upper and lower threshold voltages for the circuit are, respectively.
A
+5V and -5V
B
+7V and -3V
C
+3V and -7V
D
+3V and -3V
GATE EC 2017-SET-1   Analog Circuits
Question 8 Explanation: 


\begin{aligned} V_1&=\frac{3 \times 10+V_o \times 5}{15}=\frac{6+V_o}{3} \\ V_{UT}&=\frac{6+15}{3}=7V \\ V_{LT}&=\frac{6-15}{3}=-3V \end{aligned}
Question 9
For the circuit shown in the figure, R_{1}=R_{2}=R_{3}=1 \Omega , L=1 \mu H and C=1 \mu F. If the input V_{in}=cos(10^{6}t), then the overall voltage gain (V_{out}/V_{in}) of the circuit is __________
A
0
B
-1
C
-2
D
-3
GATE EC 2016-SET-3   Analog Circuits
Question 9 Explanation: 
\begin{aligned} H_{1}(s) &=\frac{V_{01}}{V_{i}}=1+\frac{R_{1}}{s L} \\ &=1+\frac{1}{\frac{s L}{R_{1}}}=1+\frac{1}{s \times 10^{-6}} \\ H_{2}(s) &=\frac{V_{0}}{V_{01}}=-\frac{R_{3}}{\frac{R_{2} C s+1}{C s}} \\ &=\frac{-s R_{3} C}{1+s R_{2} C} \\ &=\frac{-C s}{1+C s}=\frac{-1}{1+\frac{1}{C s}} \\ H(s) &=H_{1}(s) H_{2}(s) \\ &=\left(1+\frac{1}{s \times 10^{-6}}\right)\left(\frac{-s \times 1 \times 10^{-6}}{1+s \times 10^{-6}}\right)\\ &=-1 \end{aligned}
Question 10
An opamp has a finite open loop voltage gain of 100. Its input offset voltage V_{ios}(=+5mV) is modeled as shown in the circuit below. The amplifier is ideal in all other respects. V_{input} is 25 mV.

The output voltage (in millivolts) is ________
A
148.54
B
248.89
C
325.48
D
413.79
GATE EC 2016-SET-2   Analog Circuits
Question 10 Explanation: 
\begin{aligned} \text { Overall input } &=V_{\text {ios }}+V_{\text {input }} \\ &=5 \mathrm{mV}+25 \mathrm{mV}=30 \mathrm{mV}\\ v_{0}&=\frac{\left(1+\frac{R_{F}}{R_{1}}\right)}{1+\frac{1}{A_{a}}\left(1+\frac{R_{F}}{R_{1}}\right)} \times \text { Overall input } \\ &=\frac{1+\frac{15 \mathrm{k} \Omega}{1 \mathrm{k} \Omega}}{1+\frac{1}{100}\left(1+\frac{15 \mathrm{k} \Omega}{1 \mathrm{k} \Omega}\right)} \times 30 \times 10^{-3}=413.79 \mathrm{mv} \end{aligned}
There are 10 questions to complete.
Like this FREE website? Please share it among all your friends and join the campaign of FREE Education to ALL.