Question 1 |

A state transition diagram with states A, B, and C, and transition probabilities p_1,p_2,...,p_7 is shown in the figure (e.g., p_1 denotes the probability of transition from
state A to B). For this state diagram, select the statement(s) which is/are universally
true

p_2+p_3=p_5+p_6 | |

p_1+p_3=p_4+p_6 | |

p_1+p_4+p_7=1 | |

p_2+p_5+p_7=1 |

Question 1 Explanation:

\left.\begin{matrix}
A &\rightarrow &A &P_7 \\
A&\rightarrow &B &P_1 \\
A&\rightarrow &C &P_4
\end{matrix}\right\} \Rightarrow P_1+P_4+P_7=1

\left.\begin{matrix} B &\rightarrow &A &P_2 \\ B&\rightarrow &B &P_3 \end{matrix}\right\} \Rightarrow P_2+P_3=1

\left.\begin{matrix} C &\rightarrow &A &P_6 \\ C&\rightarrow &C &P_5 \end{matrix}\right\} \Rightarrow P_5+P_6=1

P_2+P_3=P_5+P_6\Rightarrow Option (A) is correct.

P_1+P_4+P_7=1\Rightarrow Option (C) is correct.

\left.\begin{matrix} B &\rightarrow &A &P_2 \\ B&\rightarrow &B &P_3 \end{matrix}\right\} \Rightarrow P_2+P_3=1

\left.\begin{matrix} C &\rightarrow &A &P_6 \\ C&\rightarrow &C &P_5 \end{matrix}\right\} \Rightarrow P_5+P_6=1

P_2+P_3=P_5+P_6\Rightarrow Option (A) is correct.

P_1+P_4+P_7=1\Rightarrow Option (C) is correct.

Question 2 |

For the circuit shown, the clock frequency is f_o and the duty cycle is 25%. For the
signal at the Q output of the Flip-Flop, _______.

frequency is f_0/4 and duty cycle is 50% | |

frequency is f_0/4 and duty cycle is 25% | |

frequency is f_0/2 and duty cycle is 50% | |

frequency is f_0 and duty cycle is 25% |

Question 2 Explanation:

2-bit counter

\begin{aligned} MSB&&LSB(J,K)\\ 0&&0\\ 0&&1\\ 1&&0\\ 1&&1 \end{aligned}

Duty cycle =50%

Output frequency =f_0/4

\begin{aligned} MSB&&LSB(J,K)\\ 0&&0\\ 0&&1\\ 1&&0\\ 1&&1 \end{aligned}

Duty cycle =50%

Output frequency =f_0/4

Question 3 |

The propagation delay of the exclusive-\text{OR} (\text{XOR})
gate in the circuit in the figure is 3\:ns. The propagation delay of all the flip-flops is assumed to be zero. The clock (\text{Clk})
frequency provided to the circuit is 500\: \text{MHz}.

Starting from the initial value of the flip-flop outputs Q_{2}Q_{1}Q_{0} = 1\;1\;1 with D_{2}=1, the minimum number of triggering clock edges after which the flip-flop outputs Q_{2}Q_{1}Q_{0} becomes 1\; 0\; 0 (in integer) is

Starting from the initial value of the flip-flop outputs Q_{2}Q_{1}Q_{0} = 1\;1\;1 with D_{2}=1, the minimum number of triggering clock edges after which the flip-flop outputs Q_{2}Q_{1}Q_{0} becomes 1\; 0\; 0 (in integer) is

3 | |

4 | |

5 | |

6 |

Question 3 Explanation:

\therefore\quad Total 5 clocks required.

Question 4 |

The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in the circuit shown in the figure are 4 ns, 2 ns and 1 ns, respectively.

If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is

If all the inputs P, Q, R, S and T are applied simultaneously and held constant, the maximum propagation delay of the circuit is

3 ns | |

5 ns | |

6 ns | |

7 ns |

Question 4 Explanation:

Case -1 : when T=0

Propogation delay =t_{AND1}+t_{MUX2}=2+1=3ns

Case -1 : when T=1

Propogation delay =t_{AND2}+t_{MUX1}t_{AND3}+t_{MUX2}=2+1+2+1=6ns

Propogation delay =t_{AND1}+t_{MUX2}=2+1=3ns

Case -1 : when T=1

Propogation delay =t_{AND2}+t_{MUX1}t_{AND3}+t_{MUX2}=2+1+2+1=6ns

Question 5 |

For the components in the sequential circuit shown below, t_{pd} is the propagation delay, t_{setup} is the setup time, and t_{hold} is the hold time. The maximum clock frequency (rounded
off to the nearest integer), at which the given circuit can operate reliably, is ____ MHz.

76.92 | |

46.23 | |

85.12 | |

121.23 |

Question 5 Explanation:

Total propagation delay =(t_{pd}+t_{set-up})_{max}=8ns+5ns=13ns

\therefore Frequency of operations =\frac{1000}{13}MHz=76.92MHz

\therefore Frequency of operations =\frac{1000}{13}MHz=76.92MHz

Question 6 |

The state diagram of a sequence detector is shown below. State S_0 is the initial state
of the sequence detector. If the output is 1, then

the sequence 01010 is detected | |

the sequence 01011 is detected | |

the sequence 01110 is detected | |

the sequence 01001 is detected |

Question 7 |

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12?kHz. The frequency of the signal at Q_2 is____ kHz.

2 | |

4 | |

6 | |

8 |

Question 7 Explanation:

\begin{aligned} M O D &=3 \\ f_{Q 2} &=\frac{f_{c \mid k}}{3}=\frac{12}{3} k H z=4 k H z \end{aligned}

Question 8 |

A 4-bit shift register circuit configured for right-shift operation, i.e, D_{in}\rightarrow A,\; A\rightarrow B , \; B\rightarrow C, \; C\rightarrow D, as shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.

5 | |

10 | |

15 | |

20 |

Question 8 Explanation:

So, 10 clock cycles are required.

Question 9 |

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = '0'. If the input condition is changed simultaneously to P = Q = '1', the outputs X and Y are

X = '1', Y = '1' | |

either X = '1', Y = '0' or X = '0', Y = '1' | |

either X = '1', Y = '1' or X = '0', Y = '0' | |

X = '0', Y = '0' |

Question 9 Explanation:

Present input condition : P=Q=0

\Rightarrow Corresponding outputs are X=Y=1

When input condition is changed to P=Q=1 from P=Q=0 :

Possibility - 1 :

Let gate-1 is faster than gate-2, then the possible outputs are X=0, Y=1

Possibility - 2 :

Let gate-2 is faster than gate-1, then the possible outputs are X=1, Y=0

Question 10 |

Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is___________.

20 | |

25 | |

30 | |

35 |

Question 10 Explanation:

Duty cycle of output

=\frac{\frac{T_{\mathrm{CLK}}}{2}-\frac{T_{\mathrm{CLK}}}{5}}{T_{\mathrm{CK}}} \times 100=\frac{3}{10} \times 100=30 \%

There are 10 questions to complete.