# Sequential Circuits

 Question 1
In a given sequential circuit, initial states are $Q_{1}=1$ and $Q_{2}=0$. For a clock frequency of $1 \mathrm{MHz}$, the frequency of signal $Q_{2}$ in $\mathrm{kHz}$, is ____
(rounded off to the nearest integer).

 A 200 B 500 C 250 D 750
GATE EC 2023   Digital Circuits
Question 1 Explanation:
$\begin{array}{|c|c|c|c|c|} \hline Clk & {D}_{\mathbf{1}}=\mathbf{Q}_{\mathbf{2}}[ & D_{\mathbf{2}}=\overline{\mathbf{Q}}_{\mathbf{1}} & {Q}_{\mathbf{1}} & {Q}_{\mathbf{2}} \\ \hline Initial & & & 1 & 0 \\ \hline 1 & 0 & 0 & 0 & 0 \\ 2 & 0 & 1 & 0 & 1 \\ 3 & 1 & 1 & 1 & 1 \\ 4 & 1 & 0 & 1 & 0 \\ \hline \end{array}$
Therefore, the given counter is having MOD-4
$\therefore$ The frequency of signal $Q_{2}=\frac{f_{i}}{4}=\frac{1000}{4} \mathrm{kHz}=250 \mathrm{kHz}$
 Question 2
The synchronous sequential circuit shown below works at a clock frequency of $1 \mathrm{GHz}$. The throughput, in $\mathrm{M}$ bits/s, and the latency, in ns, respectively, are

 A $1000,3$ B $333.33,1$ C $2000,3$ D $333.33,3$
GATE EC 2023   Digital Circuits
Question 2 Explanation:
The given circuit is a type of SISO.
\begin{aligned} \therefore \quad Latency &=n \times T_{\text {clk }} \ldots . .& n= \text{number of flip flops}\\ &=3 \times 1 \quad \ldots . &T_{\mathrm{clk}}=\frac{1}{f_{\mathrm{clk}}}=1 \mathrm{~ns}\\ &=3 \mathrm{~ns} & \end{aligned}
Now,
\begin{aligned} \text{Throughput}&= \text{Number of bits/sec}\\ \because \quad 1 \;bit &=1\; nsec\\ \therefore \quad \text{Throughput} &=10^{9} \mathrm{bits} / \mathrm{sec}\\ &=1000 \mathrm{Mbps} \end{aligned}

 Question 3
A state transition diagram with states A, B, and C, and transition probabilities $p_1,p_2,...,p_7$ is shown in the figure (e.g., $p_1$ denotes the probability of transition from state A to B). For this state diagram, select the statement(s) which is/are universally true

 A $p_2+p_3=p_5+p_6$ B $p_1+p_3=p_4+p_6$ C $p_1+p_4+p_7=1$ D $p_2+p_5+p_7=1$
GATE EC 2022   Digital Circuits
Question 3 Explanation:
$\left.\begin{matrix} A &\rightarrow &A &P_7 \\ A&\rightarrow &B &P_1 \\ A&\rightarrow &C &P_4 \end{matrix}\right\} \Rightarrow P_1+P_4+P_7=1$
$\left.\begin{matrix} B &\rightarrow &A &P_2 \\ B&\rightarrow &B &P_3 \end{matrix}\right\} \Rightarrow P_2+P_3=1$
$\left.\begin{matrix} C &\rightarrow &A &P_6 \\ C&\rightarrow &C &P_5 \end{matrix}\right\} \Rightarrow P_5+P_6=1$
$P_2+P_3=P_5+P_6\Rightarrow$ Option (A) is correct.
$P_1+P_4+P_7=1\Rightarrow$ Option (C) is correct.
 Question 4
For the circuit shown, the clock frequency is $f_o$ and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, _______.

 A frequency is $f_0/4$ and duty cycle is 50% B frequency is $f_0/4$ and duty cycle is 25% C frequency is $f_0/2$ and duty cycle is 50% D frequency is $f_0$ and duty cycle is 25%
GATE EC 2022   Digital Circuits
Question 4 Explanation:
2-bit counter
\begin{aligned} MSB&&LSB(J,K)\\ 0&&0\\ 0&&1\\ 1&&0\\ 1&&1 \end{aligned}

Duty cycle =50%
Output frequency =$f_0/4$
 Question 5
The propagation delay of the exclusive$-\text{OR} (\text{XOR})$ gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock $(\text{Clk})$ frequency provided to the circuit is $500\: \text{MHz}$.

Starting from the initial value of the flip-flop outputs $Q_{2}Q_{1}Q_{0} = 1\;1\;1$ with $D_{2}=1$, the minimum number of triggering clock edges after which the flip-flop outputs $Q_{2}Q_{1}Q_{0}$ becomes $1\; 0\; 0$ (in integer) is
 A 3 B 4 C 5 D 6
GATE EC 2021   Digital Circuits
Question 5 Explanation:

$\therefore\quad$Total 5 clocks required.

There are 5 questions to complete.