Question 1 |

For the components in the sequential circuit shown below, t_{pd} is the propagation delay, t_{setup} is the setup time, and t_{hold} is the hold time. The maximum clock frequency (rounded
off to the nearest integer), at which the given circuit can operate reliably, is ____ MHz.

76.92 | |

46.23 | |

85.12 | |

121.23 |

Question 1 Explanation:

Total propagation delay =(t_{pd}+t_{set-up})_{max}=8ns+5ns=13ns

\therefore Frequency of operations =\frac{1000}{13}MHz=76.92MHz

\therefore Frequency of operations =\frac{1000}{13}MHz=76.92MHz

Question 2 |

The state diagram of a sequence detector is shown below. State S_0 is the initial state
of the sequence detector. If the output is 1, then

the sequence 01010 is detected | |

the sequence 01011 is detected | |

the sequence 01110 is detected | |

the sequence 01001 is detected |

Question 3 |

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12?kHz. The frequency of the signal at Q_2 is____ kHz.

2 | |

4 | |

6 | |

8 |

Question 3 Explanation:

\begin{aligned} M O D &=3 \\ f_{Q 2} &=\frac{f_{c \mid k}}{3}=\frac{12}{3} k H z=4 k H z \end{aligned}

Question 4 |

A 4-bit shift register circuit configured for right-shift operation, i.e, D_{in}\rightarrow A,\; A\rightarrow B , \; B\rightarrow C, \; C\rightarrow D, as shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.

5 | |

10 | |

15 | |

20 |

Question 4 Explanation:

So, 10 clock cycles are required.

Question 5 |

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = '0'. If the input condition is changed simultaneously to P = Q = '1', the outputs X and Y are

X = '1', Y = '1' | |

either X = '1', Y = '0' or X = '0', Y = '1' | |

either X = '1', Y = '1' or X = '0', Y = '0' | |

X = '0', Y = '0' |

Question 5 Explanation:

Present input condition : P=Q=0

\Rightarrow Corresponding outputs are X=Y=1

When input condition is changed to P=Q=1 from P=Q=0 :

Possibility - 1 :

Let gate-1 is faster than gate-2, then the possible outputs are X=0, Y=1

Possibility - 2 :

Let gate-2 is faster than gate-1, then the possible outputs are X=1, Y=0

Question 6 |

Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is___________.

20 | |

25 | |

30 | |

35 |

Question 6 Explanation:

Duty cycle of output

=\frac{\frac{T_{\mathrm{CLK}}}{2}-\frac{T_{\mathrm{CLK}}}{5}}{T_{\mathrm{CK}}} \times 100=\frac{3}{10} \times 100=30 \%

Question 7 |

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

mod-5 counter | |

mod-6 counter | |

mod-7 counter | |

mod-8 counter |

Question 7 Explanation:

Clock frequency= 1 GHz

\Rightarrow Clock time period = 1 ns

If the propagation delay of the NANO gate were 0 ns, the circuit would have behaved as MOD 6 counter.

However, the delay of NANO gate is 2 ns. During this time, two more clock pulses would reach the counter, and therefore it would count two more states.

Hence, it acts as MOD 8 counter.

\Rightarrow Clock time period = 1 ns

If the propagation delay of the NANO gate were 0 ns, the circuit would have behaved as MOD 6 counter.

However, the delay of NANO gate is 2 ns. During this time, two more clock pulses would reach the counter, and therefore it would count two more states.

Hence, it acts as MOD 8 counter.

Question 8 |

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R= 10 k\Omega and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor R is ________

The average power dissipated (in mW) in the resistor R is ________

0.5 | |

1 | |

1.5 | |

2 |

Question 8 Explanation:

The waveform of the gate output

Average power dissipated

P=\frac{V^{2}}{R} \times \frac{T_{\mathrm{ON}}}{T}=\frac{5^{2}}{10 \mathrm{k}} \times \frac{3 T}{5 T}=1.5 \mathrm{mW}

Question 9 |

A three bit pseudo random number generator is shown. Initially the value of output
Y \equiv Y_{2} Y_{1} Y_{0} is set to 111. The value of output Y after three clock cycles is

000 | |

001 | |

010 | |

100 |

Question 9 Explanation:

The given circuit is similar to

After three clock Y is 100.

After three clock Y is 100.

Question 10 |

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset (\bar{R_{d}} input).The counter corresponding to this circuit is
(

a modulo-5 binary up counter | |

a modulo-6 binary down counter | |

a modulo-5 binary down counter | |

a modulo-6 binary up counter |

Question 10 Explanation:

Q is applied as negative edge triggering clock.

\Rightarrow Counter is up counter.

Reset signal =\overline{Q_{2} \cdot Q_{0}}

The counter resets at 101

\Rightarrow Counter is MOD-5

\Rightarrow Counter is up counter.

Reset signal =\overline{Q_{2} \cdot Q_{0}}

The counter resets at 101

\Rightarrow Counter is MOD-5

There are 10 questions to complete.