# Sequential Circuits

 Question 1
For the components in the sequential circuit shown below, $t_{pd}$ is the propagation delay, $t_{setup}$ is the setup time, and $t_{hold}$ is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is ____ MHz.
 A 76.92 B 46.23 C 85.12 D 121.23
GATE EC 2020   Digital Circuits
Question 1 Explanation:
Total propagation delay $=(t_{pd}+t_{set-up})_{max}=8ns+5ns=13ns$
$\therefore$ Frequency of operations $=\frac{1000}{13}MHz=76.92MHz$
 Question 2
The state diagram of a sequence detector is shown below. State $S_0$ is the initial state of the sequence detector. If the output is 1, then
 A the sequence 01010 is detected B the sequence 01011 is detected C the sequence 01110 is detected D the sequence 01001 is detected
GATE EC 2020   Digital Circuits
 Question 3
In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12?kHz. The frequency of the signal at $Q_2$ is____ kHz.
 A 2 B 4 C 6 D 8
GATE EC 2019   Digital Circuits
Question 3 Explanation:

\begin{aligned} M O D &=3 \\ f_{Q 2} &=\frac{f_{c \mid k}}{3}=\frac{12}{3} k H z=4 k H z \end{aligned}
 Question 4
A 4-bit shift register circuit configured for right-shift operation, i.e, $D_{in}\rightarrow A,\; A\rightarrow B , \; B\rightarrow C, \; C\rightarrow D$, as shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.
 A 5 B 10 C 15 D 20
GATE EC 2017-SET-1   Digital Circuits
Question 4 Explanation:

So, 10 clock cycles are required.
 Question 5
In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = '0'. If the input condition is changed simultaneously to P = Q = '1', the outputs X and Y are
 A X = '1', Y = '1' B either X = '1', Y = '0' or X = '0', Y = '1' C either X = '1', Y = '1' or X = '0', Y = '0' D X = '0', Y = '0'
GATE EC 2017-SET-1   Digital Circuits
Question 5 Explanation:

Present input condition : P=Q=0
$\Rightarrow$ Corresponding outputs are X=Y=1
When input condition is changed to P=Q=1 from P=Q=0 :
Possibility - 1 :
Let gate-1 is faster than gate-2, then the possible outputs are X=0, Y=1
Possibility - 2 :
Let gate-2 is faster than gate-1, then the possible outputs are X=1, Y=0
 Question 6
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is___________.
 A 20 B 25 C 30 D 35
GATE EC 2017-SET-1   Digital Circuits
Question 6 Explanation:

Duty cycle of output
$=\frac{\frac{T_{\mathrm{CLK}}}{2}-\frac{T_{\mathrm{CLK}}}{5}}{T_{\mathrm{CK}}} \times 100=\frac{3}{10} \times 100=30 \%$
 Question 7
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a
 A mod-5 counter B mod-6 counter C mod-7 counter D mod-8 counter
GATE EC 2016-SET-3   Digital Circuits
Question 7 Explanation:
Clock frequency= 1 GHz
$\Rightarrow$ Clock time period = 1 ns
If the propagation delay of the NANO gate were 0 ns, the circuit would have behaved as MOD 6 counter.
However, the delay of NANO gate is 2 ns. During this time, two more clock pulses would reach the counter, and therefore it would count two more states.
Hence, it acts as MOD 8 counter.
 Question 8
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R= 10 k$\Omega$ and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle.

The average power dissipated (in mW) in the resistor R is ________
 A 0.5 B 1 C 1.5 D 2
GATE EC 2016-SET-2   Digital Circuits
Question 8 Explanation:

The waveform of the gate output

Average power dissipated
$P=\frac{V^{2}}{R} \times \frac{T_{\mathrm{ON}}}{T}=\frac{5^{2}}{10 \mathrm{k}} \times \frac{3 T}{5 T}=1.5 \mathrm{mW}$
 Question 9
A three bit pseudo random number generator is shown. Initially the value of output $Y \equiv Y_{2} Y_{1} Y_{0}$ is set to 111. The value of output Y after three clock cycles is
 A $000$ B $001$ C $010$ D $100$
GATE EC 2015-SET-3   Digital Circuits
Question 9 Explanation:
The given circuit is similar to

After three clock Y is 100.
 Question 10
The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset ($\bar{R_{d}}$ input).The counter corresponding to this circuit is (
 A a modulo-5 binary up counter B a modulo-6 binary down counter C a modulo-5 binary down counter D a modulo-6 binary up counter
GATE EC 2015-SET-3   Digital Circuits
Question 10 Explanation:
Q is applied as negative edge triggering clock.
$\Rightarrow$ Counter is up counter.
Reset signal $=\overline{Q_{2} \cdot Q_{0}}$
The counter resets at 101
$\Rightarrow$ Counter is MOD-5
There are 10 questions to complete.