Question 1 |

A 2-bit flash Analog to Digital Converter (ADC) is given below. The input is 0 \leq V_{IN} \leq 3 Volts. The expression for the LSB of the output B_0 as a Boolean function of X_{2},X_{1} \; and \; X_{0} is

X_{0}[\overline{X_{2}\oplus X_{1}}] | |

\bar{X_{0}}[\overline{X_{2}\oplus X_{1}}] | |

X_{0}[{X_{2}\oplus X_{1}}] | |

\bar{X_{0}}[X_{2}\oplus X_{1}] |

Question 1 Explanation:

The input to digital circuuit is X_2,X_1,X_0 and output is B_1,B_0

B_0=\bar{X_2}\bar{X_1}X_0+X_2X_1X_0

\;\;=X_0(\bar{X_2}\bar{X_1}+X_2X_1)

\;\;=X_0(\overline{X_2\oplus X_1})

B_0=\bar{X_2}\bar{X_1}X_0+X_2X_1X_0

\;\;=X_0(\bar{X_2}\bar{X_1}+X_2X_1)

\;\;=X_0(\overline{X_2\oplus X_1})

Question 2 |

A temperature in the range of -40^{\circ}C to 55^{\circ}C is to be measured with a resolution of 0.1^{\circ}C. The minimum number of ADC bits required to get a matching dynamic range of the temperature sensor is

8 | |

10 | |

12 | |

14 |

Question 2 Explanation:

Temperature range of -40^{\circ}C \; to \; 55^{\circ}C

So. Total range in 95^{\circ}C

Since, resolution is 0.1^{\circ}C

So, number of steps will be 950

To have 950 steps, we need at least 10 bits.

So. Total range in 95^{\circ}C

Since, resolution is 0.1^{\circ}C

So, number of steps will be 950

To have 950 steps, we need at least 10 bits.

Question 3 |

An 8-bit, unipolar Successive Approximation Register type ADC is used to convert 3.5 V to digital equivalent output. The reference voltage is +5 V. The output of the ADC, at the end of 3rd clock pulse after the start of conversion, is

1010 0000 | |

1000 0000 | |

0000 0001 | |

1000 0000 |

Question 3 Explanation:

The reference voltage is 5 V.

The number of bits in ADC are 8.

So, the resolution will be =\frac{5}{2^8-1}=\frac{5}{255}

The applied input is 3.5 V.

The succesive approximation ADC start working from the MSB so,

After one clock:

SAR will toggle it's MSB from 0\rightarrow 1. So, output of SAR will be 1000 0000.

After second clock:

SAR will toggle its 7th bit from 0\rightarrow 1 but 1100 0000 will result in value greater than 3.5. So, output of SAR after 2nd clock will be 1000 0000.

After third clock:

SAR will toggle it's 6th bit from 0\rightarrow 1 and output will be 1010 0000.

The number of bits in ADC are 8.

So, the resolution will be =\frac{5}{2^8-1}=\frac{5}{255}

The applied input is 3.5 V.

The succesive approximation ADC start working from the MSB so,

After one clock:

SAR will toggle it's MSB from 0\rightarrow 1. So, output of SAR will be 1000 0000.

After second clock:

SAR will toggle its 7th bit from 0\rightarrow 1 but 1100 0000 will result in value greater than 3.5. So, output of SAR after 2nd clock will be 1000 0000.

After third clock:

SAR will toggle it's 6th bit from 0\rightarrow 1 and output will be 1010 0000.

Question 4 |

The Octal equivalent of HEX and number AB.CD is

253.314 | |

253.632 | |

526.314 | |

526.632 |

Question 4 Explanation:

Hex Number (AB.CD)

1010\;\;1011\;.\; 1100\;\;1101

For finding its octal number, we can add one zero in both extreme and grouping.

010\;101\;011\;.\;110\;011\;010

Its equavalent octal number is (253.632)_8

1010\;\;1011\;.\; 1100\;\;1101

For finding its octal number, we can add one zero in both extreme and grouping.

010\;101\;011\;.\;110\;011\;010

Its equavalent octal number is (253.632)_8

Question 5 |

It is required to design an anti-aliasing filter for an, 8 bit ADC. The filter is a first order RC filter with R = 1\Omega and C = 1F. The ADC is designed to span a sinusoidal signal with peak to peak amplitude equal to the full scale range of the ADC.

What is the SNR (in dB) of the ADC ? Also find the frequency (in decades) at the filter output at which the filter attenuation just exceeds the SNR of the ADC.

What is the SNR (in dB) of the ADC ? Also find the frequency (in decades) at the filter output at which the filter attenuation just exceeds the SNR of the ADC.

50 dB, 2 decade | |

50 dB, 2.5 decade | |

60 dB, 2 decade | |

60 dB, 2.5 decade |

Question 6 |

It is required to design an anti-aliasing filter for an, 8 bit ADC. The filter is a first order RC filter with R = 1\Omega and C = 1F. The ADC is designed to span a sinusoidal signal with peak to peak amplitude equal to the full scale range of the ADC.

The transfer Function of the filter and its roll off respectively are

The transfer Function of the filter and its roll off respectively are

1/(1 + RCs), - 20 dB/decade | |

(1 + RCs), - 40 dB/decade | |

1/(1+ RCs), -40 dB/decade | |

{RCs/(1+RCs)}, -20 db/decade |

Question 7 |

A student has made a 3-bit binary down counter and connected to the R-2R
ladder type DAC [Gain=(-1K\Omega/2R)] as shown in figure to generate a staircase waveform. The output achieved is different as shown in figure. What could be the possible cause of this error ?

The resistance values are incorrect option. | |

The counter is not working properly | |

The connection from the counter of DAC is not proper | |

The R and 2R resistance are interchanged |

Question 7 Explanation:

Initial stage of the counter =(111)_2=(7)_10

So output will be equal to 7 V.

Next state of counter =(110)_2=(6)_10

So output should be = 6 V

But output is 3 V that meansLSB of counter is connected to MSB of DAC and MSB of counter is connected to LSB of DAC.

Similarly next state oc counter =(101)_2=(5)_10

Input to DAC =(101)_2=(5)_10

So, output = 5V

When counter goes to (100)_2 then input to DAC =(001)_2=(1)_10

So output = 1 V

So connections are not proper.

So output will be equal to 7 V.

Next state of counter =(110)_2=(6)_10

So output should be = 6 V

But output is 3 V that meansLSB of counter is connected to MSB of DAC and MSB of counter is connected to LSB of DAC.

Similarly next state oc counter =(101)_2=(5)_10

Input to DAC =(101)_2=(5)_10

So, output = 5V

When counter goes to (100)_2 then input to DAC =(001)_2=(1)_10

So output = 1 V

So connections are not proper.

Question 8 |

The voltage comparator shown in figure can be used in the analog-to-digital
conversion as

a 1-bit quantizer | |

a 2-bit quantizer | |

a 4-bit quantizer | |

a 8-bit quantizer |

Question 8 Explanation:

Even when V_1 \gt V_2, the (o/p) 'V_0' is high and for the next case (V_1 \lt V_2) (o/p) is low.It is 1 bit quantizer. Since, it has two states which can be represented by 1 bit.

Question 9 |

A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at
the input of an ADC (analog-to-digital converter). The conversion time of the ADC
is 1\musec, and during this time, the capacitor should not lose more than 0.5% of
the charge put across it during the sampling time. The maximum value of the
input signal to the S/H circuit is 5V. The leakage current of the S/H circuit should
be less than

2.5 mA | |

0.25 mA | |

25 mA | |

2.5 mA |

Question 10 |

Among the following four, the slowest ADC (analog-to-digital converter) is

parallel comparator (i.e., flash) type | |

successive approximation type | |

integrating type | |

counting type |

There are 10 questions to complete.