Question 1 |
The Zener diode in circuit has a breakdown voltage of 5 \mathrm{~V}. The current gain \beta of the transistor in the active region in 99. Ignore baseemitter voltage drop \mathrm{V}_{\mathrm{BE}}. The current through the 20 \Omega resistance in milliamperes is ____ (Round off to 2 decimal places).
287.36 | |
145.36 | |
250 | |
547.36 |
Question 1 Explanation:
Redraw the circuit :
We know,
\begin{aligned} \mathrm{I}_{\mathrm{E}} & =(1+\beta) \mathrm{I}_{\mathrm{B}} \\ & =100 \mathrm{I}_{\mathrm{B}} \\ \Rightarrow \quad \mathrm{I}_{\mathrm{B}} & =\frac{\mathrm{I}_{\mathrm{E}}}{100} \end{aligned}
Apply KVL in loop,
\begin{aligned} & 25-\frac{\mathrm{I}_{E}}{100} \times 7000-I_{E} \times 10-I_{E} \times 20=0 \\ & \Rightarrow \quad \mathrm{I}_{\mathrm{E}}=0.25 \mathrm{~A} \text { or } 250 \mathrm{~mA} \end{aligned}
We know,
\begin{aligned} \mathrm{I}_{\mathrm{E}} & =(1+\beta) \mathrm{I}_{\mathrm{B}} \\ & =100 \mathrm{I}_{\mathrm{B}} \\ \Rightarrow \quad \mathrm{I}_{\mathrm{B}} & =\frac{\mathrm{I}_{\mathrm{E}}}{100} \end{aligned}
Apply KVL in loop,
\begin{aligned} & 25-\frac{\mathrm{I}_{E}}{100} \times 7000-I_{E} \times 10-I_{E} \times 20=0 \\ & \Rightarrow \quad \mathrm{I}_{\mathrm{E}}=0.25 \mathrm{~A} \text { or } 250 \mathrm{~mA} \end{aligned}
Question 2 |
All the elements in the circuit shown in the following figure are ideal. Which of the following statements is/are true?
When switch S is O N, both D_{1} and D_{2} conducts and D_{3} is reverse biased | |
When switch \mathrm{S} is ON, \mathrm{D}_{1} conducts and both D_{2} and D_{3} are reverse biased | |
When switch S is OF F, D_{1} is reverse biased and both D_{2} and D_{3} conduct | |
When switch S is OFF, D_{1} conducts, D_{2} is reverse biased and D_{3} conducts |
Question 2 Explanation:
Case (i): Switch \mathrm{S} is ON
Assume \mathrm{D}_{3} \rightarrow OFF, D_{2} \rightarrow OFF and \mathrm{D}_{1} \rightarrow \mathrm{ON}
Redraw the circuit :
\therefore Our assumption is correct.
Case (ii) : Switch \mathrm{S} is OFF.
Then, \mathrm{D}_{3} \rightarrow \mathrm{ON}, \mathrm{D}_{2} \rightarrow \mathrm{ON} and \mathrm{D}_{1} \rightarrow \mathrm{OFF}
Redraw the circuit :
\therefore Circuit satisfy this condition also.
Hence, option (B) and (C) will be correct.
Assume \mathrm{D}_{3} \rightarrow OFF, D_{2} \rightarrow OFF and \mathrm{D}_{1} \rightarrow \mathrm{ON}
Redraw the circuit :
\therefore Our assumption is correct.
Case (ii) : Switch \mathrm{S} is OFF.
Then, \mathrm{D}_{3} \rightarrow \mathrm{ON}, \mathrm{D}_{2} \rightarrow \mathrm{ON} and \mathrm{D}_{1} \rightarrow \mathrm{OFF}
Redraw the circuit :
\therefore Circuit satisfy this condition also.
Hence, option (B) and (C) will be correct.
Question 3 |
Consider the OP AMP based circuit shown in the figure. Ignore the conduction drops of diodes D_{1} and D_{2}. All the components are ideal and the breakdown voltage of the Zener is 5 \mathrm{~V}. Which of the following statements is true?
The maximum and minimum values of the output voltage \mathrm{V}_{0} are +15 \mathrm{~V} and -10 \mathrm{~V}, respectively. | |
The maximum and minimum values of the output voltage \mathrm{V}_{0} are +5 \mathrm{~V} and -15 \mathrm{~V}, respectively. | |
The maximum and minimum values of the output voltage \mathrm{V}_{0} are +10 \mathrm{~V} and -5 \mathrm{~V}, respectively. | |
The maximum and minimum values of the output voltage \mathrm{V}_{0} are +5 \mathrm{~V} and -10V, respectively |
Question 3 Explanation:
During positive hall cycle:
\therefore \mathrm{D}_{1} \rightarrow \mathrm{ON} and \mathrm{D}_{2} \rightarrow \mathrm{OFF}
Redraw the circuit :
\therefore V_0=-V_i
\quad (V_0)_{min}=-10V
During negative half cycle :
\mathrm{V}^{+} \gt \mathrm{V}^{-}
Zener diode \rightarrow ON, \mathrm{D}_{1} \rightarrow OFF and \mathrm{D}_{2} \rightarrow \mathrm{ON}
Redraw the circuit:
\therefore \quad (V_0)_{max}=5V
\therefore \mathrm{D}_{1} \rightarrow \mathrm{ON} and \mathrm{D}_{2} \rightarrow \mathrm{OFF}
Redraw the circuit :
\therefore V_0=-V_i
\quad (V_0)_{min}=-10V
During negative half cycle :
\mathrm{V}^{+} \gt \mathrm{V}^{-}
Zener diode \rightarrow ON, \mathrm{D}_{1} \rightarrow OFF and \mathrm{D}_{2} \rightarrow \mathrm{ON}
Redraw the circuit:
\therefore \quad (V_0)_{max}=5V
Question 4 |
The current gain (I_{out}/I_{in}) in the circuit with an ideal current amplifier given below
is
\frac{C_f}{C_c} | |
\frac{-C_f}{C_c} | |
\frac{C_c}{C_f} | |
\frac{-C_c}{C_f} |
Question 4 Explanation:
Redraw the circuit:
From circuit,
\begin{aligned} V_o&=V_c \\ &=\frac{1}{C_f}\int I_{in}dt \\ I_{out}&=C_c\frac{dV_o}{dt} \\ &= C_c\frac{d}{dt}\left ( \frac{1}{C_f} \int I_{in}dt\right )\\ &=\frac{C_c}{C_f}I_{in}\\ \Rightarrow \frac{I_{out}}{I_{in}}&=\frac{C_c}{C_f} \end{aligned}
From circuit,
\begin{aligned} V_o&=V_c \\ &=\frac{1}{C_f}\int I_{in}dt \\ I_{out}&=C_c\frac{dV_o}{dt} \\ &= C_c\frac{d}{dt}\left ( \frac{1}{C_f} \int I_{in}dt\right )\\ &=\frac{C_c}{C_f}I_{in}\\ \Rightarrow \frac{I_{out}}{I_{in}}&=\frac{C_c}{C_f} \end{aligned}
Question 5 |
The output impedance of a non-ideal operational amplifier is denoted by Z_{out} . The
variation in the magnitude of Z_{out} with increasing frequency, f , in the circuit shown
below, is best represented by
A | |
B | |
C | |
D |
Question 5 Explanation:
Bode plot of negative feedback amplifier:
Given amplifier is a voltage series feedback amplifier.
Therefore, Output impedance is given by
Z_{out}=\frac{Z_o}{1+A\beta } =\frac{Z_o}{1+A } \;\;\;(\beta=1 \text{ for buffer})
From Bode plot ; at low frequency, the open loop gain (A) is constant.
when \omega \uparrow, A \downarrow,Z_{out}\uparrow
At A=0, Z_{out}=Z_o\rightarrow constant
Therefore, z_{out} with frequency represented by
Given amplifier is a voltage series feedback amplifier.
Therefore, Output impedance is given by
Z_{out}=\frac{Z_o}{1+A\beta } =\frac{Z_o}{1+A } \;\;\;(\beta=1 \text{ for buffer})
From Bode plot ; at low frequency, the open loop gain (A) is constant.
when \omega \uparrow, A \downarrow,Z_{out}\uparrow
At A=0, Z_{out}=Z_o\rightarrow constant
Therefore, z_{out} with frequency represented by
There are 5 questions to complete.