# Analog Electronics

 Question 1
The temperature of the coolant oil bath for a transformer is monitored using the circuit shown. It contains a thermistor with a temperature-dependent resistance, $R_{thermistor} = 2(1 + \alpha T) k\Omega$. Where T is the temperature in $^{\circ}C$. The temperature coefficient $\alpha$, is $-(4 \pm 0.25) \%/^{\circ}C$. Circuit parameters: $R_1 = 1 k\Omega , R_2 = 1.3 k\Omega , R_3 = 2.6 k\Omega$. The error in the output signal (in V. rounded off lo 2 decimal places) at 150$^{\circ}C$ is ________.
 A 0.01 B 0.08 C 0.04 D 0.06
GATE EE 2020      Operational Amplifiers
Question 1 Explanation:
As per GATE official answer key MTA (Marks to ALL)
\begin{aligned} \text{Given data,}\\ R_{thermistor}&=R_{th}=2(1+\alpha T)K\Omega \\ \alpha &=-(4+0.25)\%/^{\circ}C=-(0.04\pm 0.0025)^{\circ}C \\ \alpha _{max}&=-0.0424/^{\circ}C, \; \; \alpha _{min}=-0.375/^{\circ}C\\ \text{Temperature, } T&=150^{\circ}C \\ R_{1}&=1 K\Omega ,\; R_{2}=1.3 K\Omega , \; R_{3}=2.6 K\Omega\\ \text{Considering, }\alpha &=-0.04 \\ R_{th}&=2[1-0.04\times 150]=-10 K\Omega \\ V_{0}&=V_{1}\times \frac{R_{1}}{R_{1}+R_{th}}\left [ 1+\frac{R_{2}}{R_{3}} \right ]\\ &=3\times \frac{1k}{1k+10k}\left [ 1+\frac{1.3k}{2.6k} \right ] \\ &=-0.5 V \\ \text{Case-1:} \\ \text{Considering, }\alpha _{max}&=-0.0425/^{\circ}C \\ R_{thmax}&=2[1+(-0.0425)\times 150] =-10.75\, k\Omega \\ V_{0}&=V_{1}\times \frac{R_{1}}{R_{1}+R_{th}}\left [ 1+\frac{R_{2}}{R_{3}} \right ]\\ &=3\times \frac{1k}{1k-10.75k}\left [ 1+\frac{1.3k}{2.6k} \right ] \\ &=-0.46 V \\ \text{Case-2:} \\ \text{Considering, }\alpha _{min}&=-0.0375/^{\circ}C \\ R_{thmin}&=2[1+(-0.0375)\times 150] =-9.25\, k\Omega \\ V_{0} &=3\times \frac{1k}{1k-9.25k}\left [ 1+\frac{1.3k}{2.6k} \right ] \\ &=-0.54 V \\ \text{Output voltage, }\\ V_0&=0.5\pm0.04 \; \Rightarrow \; \text{Error}=0.04 \end{aligned}
 Question 2
The cross-section of a metal-oxide-semiconductor structure is shown schematically. Starting from an uncharged condition, a bias of +3V is applied to the gate contact with respect to the body contact. The charge inside the silicon dioxide layer is then measured to be +Q. The total charge contained within the dashed box shown, upon application of bias, expressed as a multiple of Q (absolute value in Coulombs, rounded off to the nearest integer) is __________ .
 A 0 B 1 C -1 D 2
GATE EE 2020      BJT, FET and their Biasing Circuits
Question 2 Explanation:

Overall charge in side the box $q + q - q - q = 0$ charge
 Question 3
A common-source amplifier with a drain resistance, $R_D = 4.7 k\Omega$, is powered using a 10 V power supply. Assuming that the transconductance, $g_m, \;is\; 520 \mu A/V$, the voltage gain of the amplifier is closest to:
 A -2.44 B -1.22 C 1.22 D 2.44
GATE EE 2020      Operational Amplifiers
Question 3 Explanation:
Given data:
$R_{D}=4.7 K\Omega ,\; g_{m}=520 \mu A/V$
Voltage gain of CS amplifier
$=-g_{m}R_{D}=-520\, \mu A/V\, \times \, 4.7\, k\Omega =-2.44$
 Question 4
In the circuit below, the operational amplifier is ideal. If $V_1$=10 mV and $V_2$=50 mV, the output voltage ($V_{out}$) is
 A 100 mV B 400 mV C 500 mV D 600 mV
GATE EE 2019      Operational Amplifiers
Question 4 Explanation:

$V_o=\frac{R_2}{R_1}(V_2-V_1)$
$\;\;=\frac{100k}{10k}(50\; mV-10\; mV)$
$\;\;=10(40\; mV)=400\;mV$
 Question 5
The enhancement type MOSFET in the circuit below operates according to the square law. $\mu_nC_{ox}=100\mu A/V^2$, the threshold voltage ($V_T$) is 500 mV. Ignore channel length modulation. The output voltage $V_{out}$ is
 A 100 mV B 500 mV C 600 mV D 2 V
GATE EE 2019      BJT, FET and their Biasing Circuits
Question 5 Explanation:

As, $V_{DS}=V_{GS}$
MOSFET is in saturation,
\begin{aligned} I_D&=\frac{1}{2}\mu _nC_{Ox}\left ( \frac{W}{L} \right )(V_{GS}-V_T)^2 \\ 5 \times 10^{-6}&=\frac{1}{2} \times 100 \times 10^{-6} \times 10 (V_{GS}-0.5)^2\\ V_{GS}&=0.6 \\ V_0&=600mV \end{aligned}
 Question 6
A current controlled current source (CCCS) has an input impedance of 10 $\Omega$ and output impedance of 100 k$\Omega$. When this CCCS is used in a negative feedback closedloop with a loop gain of 9, the closed loop output impedance is
 A 10$\Omega$ B 100$\Omega$ C 100k$\Omega$ D 1000k$\Omega$
GATE EE 2019      Oscillators and Feedback Amplifiers
Question 6 Explanation:
"CCCS" (Current controlled current source amplifier)
Given, $Z_0=100k\Omega$
Loop gain, $A\beta =9$
$Z_{0F}=Z_0[1+A\beta ] \;\;\;(\text{High impedance CS})$
$=100k\Omega [1+9]$
$=100k\Omega \times 10$
$=1000k\Omega$
 Question 7
Given, $V_{gs}$ is the gate-source voltage, $V_{ds}$ is the drain source voltage, and $V_{th}$ is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are
 A $V_{gs} \lt V_{th};V_{ds}\geq V_{gs}-V_{th}$ B $V_{gs} \gt V_{th};V_{ds}\geq V_{gs}-V_{th}$ C $V_{gs} \gt V_{th};V_{ds}\leq V_{gs}-V_{th}$ D $V_{gs} \lt V_{th};V_{ds}\leq V_{gs}-V_{th}$
GATE EE 2019      BJT, FET and their Biasing Circuits
Question 7 Explanation:
For NMOS transistor to be in saturation the condition will be
$V_{gs} \gt V_{th}$
and $V_{ds} \geq V_{gs}-V_{th}$
 Question 8
In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain $\beta=100$. The base-emitter voltage drop is a constant, $V_{BE}= 0.7$ V. The value of the The venin equivalent resistance $R_{Th}$ (in $\Omega$) as shown in the figure is ______ (up to 2 decimal places).
 A 70.45 B 85.25 C 90.09 D 105.65
GATE EE 2018      BJT, FET and their Biasing Circuits
Question 8 Explanation:

To calculate $R_{Th}$ D.C. volatage should be short circuited.

$R_{Th}=1k\Omega ||\frac{10k}{1+\beta }$
$\; \; =1k\Omega ||99.0099$
$R_{Th}=90.09\Omega$
 Question 9
The op-amp shown in the figure is ideal. The input impedance $\frac{v_{in}}{i_{in}}$ is given by
 A $Z\frac{R_{1}}{R_{2}}$ B $-Z\frac{R_{1}}{R_{2}}$ C Z D $Z\frac{R_{1}}{R_{1}+R_{2}}$
GATE EE 2018      Operational Amplifiers
Question 9 Explanation:
According to virtual ground,
\begin{aligned} V_A&=V_B=V_{in} \\ \text{At node A,} \\ \frac{V_{in}-V_o}{Z}&=i_{in}\;\; ...(i) \\ V_{in}&=\left [ \frac{1}{R_2}+\frac{1}{R_1} \right ]=\frac{V_o}{R_1} \\ V_{in}\left [ \frac{R_1+R_2}{R_1R_2} \right ] \times R_1&=V_o \\ V_o&=V_{in} \times \left [ \frac{R_1+R_2}{R_2} \right ] \;\;...(ii)\\ \text{Equation (ii)}& \text{ in euation (i), }\\ \frac{V_{in}-V_o}{Z}&=i_{in} \\ \frac{V_{in}-V_{in}\left [ \frac{R_1+R_2}{R_2} \right ]}{Z}&=i_{in} \\ \frac{V_{in}}{i_{in}}\left [ 1-\frac{R_1+R_2}{R_2} \right ]&=Z \\ \frac{V_{in}}{i_{in}}\left [\frac{R_2-R_1+R_2}{R_2} \right ]&=Z \\ \frac{V_{in}}{i_{in}}&=-Z\cdot \frac{R_2}{R_1} \end{aligned}
 Question 10
For the circuit shown below, assume that the OPAMP is ideal.

Which one of the following is TRUE?
 A $v_o=v_s$ B $v_o=1.5v_s$ C $v_o=2.5v_s$ D $v_o=5v_s$
GATE EE 2017-SET-2      Operational Amplifiers
Question 10 Explanation:

$V_A=\frac{V_s}{2}$
$I_3=\frac{V_A}{R}=\frac{V_s}{2R}$
$V_B-V_A=I_3R$
$V_B=V_A+I_3R=\frac{V_s}{2}+\frac{V_s}{2}=V_s$
$I_2=\frac{V_B}{R}=\frac{V_s}{R}$
$I_1=I_2+I_3$
$\;\;=\frac{V_s}{R}+\frac{V_s}{2R}=\frac{V_s}{R}[1.5]$
$V_0-V_B=I_1R$
$\Rightarrow V_0=V_B+\frac{V_s}{R}[1.5]R$
$\;\;\;=V_s+1.5V_s=2.5V_s$

There are 10 questions to complete.