BJT, FET and their Biasing Circuits

Question 1
The cross-section of a metal-oxide-semiconductor structure is shown schematically. Starting from an uncharged condition, a bias of +3V is applied to the gate contact with respect to the body contact. The charge inside the silicon dioxide layer is then measured to be +Q. The total charge contained within the dashed box shown, upon application of bias, expressed as a multiple of Q (absolute value in Coulombs, rounded off to the nearest integer) is __________ .
A
0
B
1
C
-1
D
2
GATE EE 2020   Analog Electronics
Question 1 Explanation: 



Overall charge in side the box q + q - q - q = 0 charge
Question 2
The enhancement type MOSFET in the circuit below operates according to the square law. \mu_nC_{ox}=100\mu A/V^2, the threshold voltage (V_T) is 500 mV. Ignore channel length modulation. The output voltage V_{out} is
A
100 mV
B
500 mV
C
600 mV
D
2 V
GATE EE 2019   Analog Electronics
Question 2 Explanation: 


As, V_{DS}=V_{GS}
MOSFET is in saturation,
\begin{aligned} I_D&=\frac{1}{2}\mu _nC_{Ox}\left ( \frac{W}{L} \right )(V_{GS}-V_T)^2 \\ 5 \times 10^{-6}&=\frac{1}{2} \times 100 \times 10^{-6} \times 10 (V_{GS}-0.5)^2\\ V_{GS}&=0.6 \\ V_0&=600mV \end{aligned}
Question 3
Given, V_{gs} is the gate-source voltage, V_{ds} is the drain source voltage, and V_{th} is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are
A
V_{gs} \lt V_{th};V_{ds}\geq V_{gs}-V_{th}
B
V_{gs} \gt V_{th};V_{ds}\geq V_{gs}-V_{th}
C
V_{gs} \gt V_{th};V_{ds}\leq V_{gs}-V_{th}
D
V_{gs} \lt V_{th};V_{ds}\leq V_{gs}-V_{th}
GATE EE 2019   Analog Electronics
Question 3 Explanation: 
For NMOS transistor to be in saturation the condition will be
V_{gs} \gt V_{th}
and V_{ds} \geq V_{gs}-V_{th}
Question 4
In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain \beta=100. The base-emitter voltage drop is a constant, V_{BE}= 0.7 V. The value of the The venin equivalent resistance R_{Th} (in \Omega) as shown in the figure is ______ (up to 2 decimal places).
A
70.45
B
85.25
C
90.09
D
105.65
GATE EE 2018   Analog Electronics
Question 4 Explanation: 


To calculate R_{Th} D.C. volatage should be short circuited.

R_{Th}=1k\Omega ||\frac{10k}{1+\beta }
\; \; =1k\Omega ||99.0099
R_{Th}=90.09\Omega
Question 5
For the circuit shown in the figure below, it is given that V_{CE}=\frac{V_{CC}}{2}. The transistor has \beta =29 and V_{BE}=0.7V when the B-E junction is forward biased.

For this circuit, the value of \frac{R_B}{R} is
A
43
B
92
C
121
D
129
GATE EE 2017-SET-2   Analog Electronics
Question 5 Explanation: 
In the input loop,
10=(1+\beta )I_B \times 4R+I_B \times R_B+0.7+(1+\beta )I_B \times R
10=30I_B \times 4R+I_B \times R_B+0.7+30 \times I_B \times R
9.3=150 \times I_B \times R +I_B \times R_B .....(i)

Ouput loop,
10=(1+\beta )I_B \times 4R+5V+(1+\beta )I_B \times R
5=30I_B \times 4R+30 \times I_B \times R
5=150 \times I_B \times R .....(ii)

using equation (i) and (ii),
I_BR_B=9.3-5=4.3
and simultaneously putting value of I_B R from equation (ii) in equation (i),
9.3=I_BR\left [ 150+\frac{R_B}{R} \right ]
9.3=\frac{5}{150}\left [ 150+\frac{R_B}{R} \right ]
279=150+\frac{R_B}{R}
\frac{R_B}{R}=129
Question 6
The circuit shown in the figure uses matched transistors with a thermal voltage V_T=25mV. The base currents of the transistors are negligible. The value of the resistance R in k\Omega that is required to provide 1\muA bias current for the differential amplifier block shown is ______.
A
25.4
B
50.5
C
172.7
D
256.4
GATE EE 2017-SET-1   Analog Electronics
Question 6 Explanation: 


V_{BE1}=V_{BE2}+I_0R
I_0R=V_{BE1}-V_{BE2} =V_I ln\left ( \frac{I_R}{I_3} \right )-V_T ln \left ( \frac{I_0}{I_3} \right )
where, I_s\rightarrow Reverse saturation current
R=\frac{V_T ln\left ( \frac{I_R}{I_0} \right )}{I_0}=\frac{0.025 ln\left ( \frac{1mA}{1\mu A} \right )}{1\mu A} =\frac{0.025 ln (10^3)}{1\mu A}=172.7 k\Omega
Question 7
A transistor circuit is given below. The Zener diode breakdown voltage is 5.3 V as shown. Take base to emitter voltage drop to be 0.6 V. The value of the current gain \beta is _________.
A
2.7
B
12
C
19
D
28
GATE EE 2016-SET-1   Analog Electronics
Question 7 Explanation: 


V_B=5.3 V
V_E=V_B-0.6=4.7V
I_E=\frac{V_E}{470\Omega }=10mA
I_1=\frac{10-5.3}{4.7k}=1mA
I_B=I_1-I_2=0.5mA
\frac{I_E}{I_B}=\beta +1=20
\beta =19
Question 8
When a bipolar junction transistor is operating in the saturation mode, which one of the following statements is TRUE about the state of its collector-base (CB) and the base-emitter (BE) junctions?
A
The CB junction is forward biased and the BE junction is reverse biased.
B
The CB junction is reverse biased and the BE junction is forward biased.
C
Both the CB and BE junctions are forward biased.
D
Both the CB and BE junctions are reverse biased.
GATE EE 2015-SET-2   Analog Electronics
Question 9
In the following circuit, the transistor is in active mode and V_{C}=2 V. To get V_{C}=4 V, we replace R_{C} with R^{'}_{C} . Then the ratio R^{'}_{C}/R_{C} is ______.
A
0.5
B
0.75
C
1
D
1.25
GATE EE 2015-SET-2   Analog Electronics
Question 9 Explanation: 
CASE-I:

V_C=2V
i_C=\frac{10-2}{R_C} ......(i)
10-i_BR_B-0.7=0
i_B=\frac{10-0.7}{R_B} .......(ii)

CASE-II

when V_C=4V
R_C\rightarrow R'_C
i_C=\frac{10-4}{R'_C} .....(iii)
From above equation (iii) and (i),
\frac{10-4}{R'_C}= \frac{10-2}{R_C}
\Rightarrow \frac{R'_C}{R_C}=\frac{6}{8}=\frac{3}{4}=0.75
Question 10
In the given circuit, the silicon transistor has \beta=75 and a collector voltage V_c=9 V. Then the ratio of R_{B} and R_{C} is ________.
A
75.25
B
105.13
C
150.36
D
175.45
GATE EE 2015-SET-1   Analog Electronics
Question 10 Explanation: 
Consider the circuit shown in figure.

V_C=9V
So,\;\; \frac{15-9}{R_C}=I_E
\frac{6}{R_C}=I_E
and \;\;\frac{9-0.7}{R_B}=I_B
So,\;\;\frac{8.3}{R_B}=I_B
So, \;\; \frac{I_E}{I_B}=\frac{6 \times R_B}{R_C \times 8.3}
(\beta +1)=\frac{R_B \times 6}{R_C \times 8.3}
\frac{R_B}{R_C}=105.13
There are 10 questions to complete.
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