Question 1 |
All the elements in the circuit shown in the following figure are ideal. Which of the following statements is/are true?
When switch S is O N, both D_{1} and D_{2} conducts and D_{3} is reverse biased | |
When switch \mathrm{S} is ON, \mathrm{D}_{1} conducts and both D_{2} and D_{3} are reverse biased | |
When switch S is OF F, D_{1} is reverse biased and both D_{2} and D_{3} conduct | |
When switch S is OFF, D_{1} conducts, D_{2} is reverse biased and D_{3} conducts |
Question 1 Explanation:
Case (i): Switch \mathrm{S} is ON
Assume \mathrm{D}_{3} \rightarrow OFF, D_{2} \rightarrow OFF and \mathrm{D}_{1} \rightarrow \mathrm{ON}
Redraw the circuit :
\therefore Our assumption is correct.
Case (ii) : Switch \mathrm{S} is OFF.
Then, \mathrm{D}_{3} \rightarrow \mathrm{ON}, \mathrm{D}_{2} \rightarrow \mathrm{ON} and \mathrm{D}_{1} \rightarrow \mathrm{OFF}
Redraw the circuit :
\therefore Circuit satisfy this condition also.
Hence, option (B) and (C) will be correct.
Assume \mathrm{D}_{3} \rightarrow OFF, D_{2} \rightarrow OFF and \mathrm{D}_{1} \rightarrow \mathrm{ON}
Redraw the circuit :
\therefore Our assumption is correct.
Case (ii) : Switch \mathrm{S} is OFF.
Then, \mathrm{D}_{3} \rightarrow \mathrm{ON}, \mathrm{D}_{2} \rightarrow \mathrm{ON} and \mathrm{D}_{1} \rightarrow \mathrm{OFF}
Redraw the circuit :
\therefore Circuit satisfy this condition also.
Hence, option (B) and (C) will be correct.
Question 2 |
In the \text{BJT}
circuit shown, beta of the \text{PNP}
transistor is 100. Assume V_{\text{BE}}=-0.7\;V. The voltage across R_{c}
will be \text{5 V}
when R_{2}
is __________ k \Omega.
(Round off to 2 decimal places.)
(Round off to 2 decimal places.)
84.25 | |
8.25 | |
17.06 | |
22.04 |
Question 2 Explanation:
\begin{aligned} I_{C}&=\frac{5 \mathrm{~V}}{3.3 \mathrm{k}}=1.515 \mathrm{~mA} \\ I_{E}&=1.53 \mathrm{~mA} \\ I_{B}&=0.0151 \mathrm{~mA}\\ -12+1.2 \mathrm{k} \times 1.53 \mathrm{~m}+& 0.7+V_{B}=0 \\ V_{B} &=9.464 \mathrm{~V} \\ I_{x} &=\frac{12-V_{B}}{4.7 \mathrm{k}}=\frac{12-9.464}{4.7 \mathrm{k}}=0.539 \mathrm{~mA} \\ I_{x}+I_{B} &=I_{y} \\ \Rightarrow \qquad\qquad I_{y} &=0.5396+0.0151 \\ I_{y} &=0.5546 \mathrm{~mA} \\ V_{B} &=0.5546 \mathrm{~m} \times R_{2}=9.464 \\ R_{2} &=17.06 \mathrm{k} \Omega \end{aligned}
Question 3 |
The cross-section of a metal-oxide-semiconductor structure is shown schematically.
Starting from an uncharged condition, a bias of +3V is applied to the gate contact with
respect to the body contact. The charge inside the silicon dioxide layer is then measured
to be +Q. The total charge contained within the dashed box shown, upon application
of bias, expressed as a multiple of Q (absolute value in Coulombs, rounded off to the
nearest integer) is __________ .
0 | |
1 | |
-1 | |
2 |
Question 3 Explanation:
Overall charge in side the box q + q - q - q = 0 charge
Question 4 |
The enhancement type MOSFET in the circuit below operates according to the square law. \mu_nC_{ox}=100\mu A/V^2, the threshold voltage (V_T) is 500 mV. Ignore channel length modulation. The output voltage V_{out} is
100 mV | |
500 mV | |
600 mV | |
2 V |
Question 4 Explanation:
As, V_{DS}=V_{GS}
MOSFET is in saturation,
\begin{aligned} I_D&=\frac{1}{2}\mu _nC_{Ox}\left ( \frac{W}{L} \right )(V_{GS}-V_T)^2 \\ 5 \times 10^{-6}&=\frac{1}{2} \times 100 \times 10^{-6} \times 10 (V_{GS}-0.5)^2\\ V_{GS}&=0.6 \\ V_0&=600mV \end{aligned}
Question 5 |
Given, V_{gs} is the gate-source voltage, V_{ds} is the drain source voltage, and V_{th} is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are
V_{gs} \lt V_{th};V_{ds}\geq V_{gs}-V_{th} | |
V_{gs} \gt V_{th};V_{ds}\geq V_{gs}-V_{th} | |
V_{gs} \gt V_{th};V_{ds}\leq V_{gs}-V_{th} | |
V_{gs} \lt V_{th};V_{ds}\leq V_{gs}-V_{th} |
Question 5 Explanation:
For NMOS transistor to be in saturation the condition will be
V_{gs} \gt V_{th}
and V_{ds} \geq V_{gs}-V_{th}
V_{gs} \gt V_{th}
and V_{ds} \geq V_{gs}-V_{th}
There are 5 questions to complete.