Question 1 |
In a given 8-bit general purpose micro-controller there are following flags.
C-Carry, A-Auxiliary Carry, O-Overflow flag, PParity ( 0 for even, 1 for odd) R0 and R 1 are the two general purpose registers of the microcontroller.
After execution of the following instructions, the decimal equivalent of the binary sequence of the flag pattern [CAOP] will be
MOV R0, +0x60
MOV R1, +0x46
ADD R0, R 1
C-Carry, A-Auxiliary Carry, O-Overflow flag, PParity ( 0 for even, 1 for odd) R0 and R 1 are the two general purpose registers of the microcontroller.
After execution of the following instructions, the decimal equivalent of the binary sequence of the flag pattern [CAOP] will be
MOV R0, +0x60
MOV R1, +0x46
ADD R0, R 1
1 | |
2 | |
3 | |
7 |
Question 1 Explanation:
MOV R_{0},+0 \times 60 \Rightarrow R_{0} \leftarrow 60 \mathrm{H}
MOV R_{1},+0 \times 46 \Rightarrow \mathrm{R}_{1} \leftarrow 46 \mathrm{H}
ADD R_{0}, R_{1} :
\begin{array}{lllllllll} 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & \rightarrow 46 \mathrm{H} \\ \hline 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & \rightarrow \mathrm{A} 6 \mathrm{H} \\ \hline \end{array}
Now, carry flag (C Y)=0
Auxiliary carry (\mathrm{AC})=0
\left[\because\right. No carry fro D_{3} to \left.D_{4}\right]
\because \mathrm{MSB}=1, overflow flag =1
P=0[\because Four 1's i.e. even numb
er ] \therefore Required Flag patter =[ CAOP ]
=[0010]_{2}=2
MOV R_{1},+0 \times 46 \Rightarrow \mathrm{R}_{1} \leftarrow 46 \mathrm{H}
ADD R_{0}, R_{1} :
\begin{array}{lllllllll} 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & \rightarrow 46 \mathrm{H} \\ \hline 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & \rightarrow \mathrm{A} 6 \mathrm{H} \\ \hline \end{array}
Now, carry flag (C Y)=0
Auxiliary carry (\mathrm{AC})=0
\left[\because\right. No carry fro D_{3} to \left.D_{4}\right]
\because \mathrm{MSB}=1, overflow flag =1
P=0[\because Four 1's i.e. even numb
er ] \therefore Required Flag patter =[ CAOP ]
=[0010]_{2}=2
Question 2 |
Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is
4 | |
8 | |
16 | |
32 |
Question 2 Explanation:
Redraw the circuit :
From circuit :
\begin{array}{c|ccc|cccc} & & & &\overline{\mathrm{Q}_{2}} & \mathrm{Q}_{2} & \overline{\mathrm{Q}}_{1} & \mathrm{Q}_{1} \oplus \mathrm{Q}_{2} \\ \mathrm{CLK} & \mathrm{D} & \mathrm{Q}_{1} & \mathrm{Q}_{0} & \mathrm{~A} & \mathrm{~B} & \mathrm{C} & \mathrm{D} \\ \hline 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 2 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ \hline \end{array}
\therefore \quad A B C D=(1000)_{2}=(8)_{10}
From circuit :
\begin{array}{c|ccc|cccc} & & & &\overline{\mathrm{Q}_{2}} & \mathrm{Q}_{2} & \overline{\mathrm{Q}}_{1} & \mathrm{Q}_{1} \oplus \mathrm{Q}_{2} \\ \mathrm{CLK} & \mathrm{D} & \mathrm{Q}_{1} & \mathrm{Q}_{0} & \mathrm{~A} & \mathrm{~B} & \mathrm{C} & \mathrm{D} \\ \hline 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 2 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ \hline \end{array}
\therefore \quad A B C D=(1000)_{2}=(8)_{10}
Question 3 |
An 8-bit ADC converts analog voltage in the range of 0 to +5 \mathrm{~V} to the corresponding digital code as per the conversion characteristics shown in figure. For \mathrm{V}_{\text {in }}=1,9922 \mathrm{~V}, which of the following digital output, given in hex is true?
64 \mathrm{H} | |
65 \mathrm{H} | |
66 \mathrm{H} | |
67 \mathrm{H} |
Question 3 Explanation:
Resolution =\frac{V_{F S}}{2^{n}-1}=\frac{5}{2^{8}-1}=0.0196 \mathrm{~V}
Now, No. of step =\frac{\mathrm{V}_{\text {in }}}{\text { Resolution }} =\frac{1.9922}{0.0196}=(101.64)_{10}
For (101)_{10} the analog input is less than 1.9922 \mathrm{~V}.
So, here we take (102)_{10}.
\therefore \quad(102)_{10}=66 \mathrm{H}
Now, No. of step =\frac{\mathrm{V}_{\text {in }}}{\text { Resolution }} =\frac{1.9922}{0.0196}=(101.64)_{10}
For (101)_{10} the analog input is less than 1.9922 \mathrm{~V}.
So, here we take (102)_{10}.
\therefore \quad(102)_{10}=66 \mathrm{H}
Question 4 |
The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flipflops, with each flip-flop having a propagation delay of 20 ns, is ___________.
(round off to one decimal place)
15.5 | |
20.4 | |
12.5 | |
8.6 |
Question 4 Explanation:
f_{max}=\frac{1}{nt_p}=\frac{1}{4 \times 20 \times 10^{-9}}=12.50MHz
Question 5 |
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______
counter. (in integer)
5 | |
10 | |
50 | |
25 |
Question 5 Explanation:
Overall MOD = 2 x 5 = 10
There are 5 questions to complete.