Digital Electronics

Question 1
An 8085 microprocessor accesses two memory locations (2001 H) and (2002H), that contain 8-bit numbers 98H and B1H respectively. The following program is executed:

LXI H, 2001 H
MVIA, 21H
INX H
ADD M
INX H
MOV M, A
HLT

At the end of this program, the memory location 2003H contains the number in decimal (base 10) form ________
A
200
B
21
C
210
D
221
GATE EE 2020      Microprocessors
Question 1 Explanation: 
\begin{aligned} LXI H, 2001 H & \rightarrow [HL] \rightarrow 2001 H \\MVI A, 21 H & \rightarrow [A] \leftarrow 21 H \\INX H & \rightarrow [HL] \rightarrow 2002 H \\ ADD M & \rightarrow [A] + [2002] \rightarrow [A] \\ &= (21H + B1 H) \rightarrow [A] \\ &= D2 H \rightarrow [A] \\ INX H & \rightarrow [HL] \rightarrow 2003 H \\ MOV M, A & \rightarrow [2003] \leftarrow [A] \\ [2003] &= D2 H = (1101\; 0010)_2 \\ &= 1 \times 2^7+1\times 2^6+1\times 2^4 +1\times 2^1 \\&= 128 + 64 + 16 + 2 \\&= 210 \end{aligned}
Question 2
A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0):

what is the output of this detector?
A
1,1,0,0,0,0,1,1,0,1,0,0
B
0,1,0,0,0,0,0,1,0,1,0,0
C
0,1,0,0,0,0,0,1,0,1,1,0
D
0,1,0,0,0,0,0,0,1,0,0,0
GATE EE 2020      Sequential Logic Circuits
Question 2 Explanation: 
Given overlapping sequence input data = 11010011010110
It will give output 1 when 101 is detected.
\begin{aligned} 110 - 0\\ 101 - 1\\ 010 - 0\\ 100 - 0\\ 001 - 0\\ 011 - 0\\ 110 - 0\\ 101 - 1\\ 010 - 0\\ 101 - 1\\ 011 - 0\\ 110 - 0\\ \end{aligned}
So, output = 010000010100
Question 3
In the circuit shown below, X and Y are digital inputs, and Z is a digital output. The equivalent circuit is a
A
NAND gate
B
NOR gate
C
XOR gate
D
XNOR gate
GATE EE 2019      Logic Gates
Question 3 Explanation: 
The Boolean expression for the output of the digital circuit is shown below

The above expression is of XOR gate.
Question 4
The output expression for the Karnaugh map shown below is
A
Q\bar{R}+S
B
Q\bar{R}+\bar{S}
C
QR+S
D
QR+\bar{S}
GATE EE 2019      Boolean Algebra and Minimization
Question 4 Explanation: 


Output=Q\bar{R}+S
Question 5
Digital input signals A,B,C with A as the MSB and C as the LSB are used to realize the Boolean function
F=m_{0}+m_{2}+m_{3}+m_{5}+m_{7}, \; where \; m_{i}
denotes the i^{th} minterm. In addition, F has a don't care for m_1. The simplified expression for F is given by
A
\bar{A}\bar{C}+\bar{B}C+AC
B
\bar{A}+C
C
\bar{C}+A
D
\bar{A}C+BC+A\bar{C}
GATE EE 2018      Boolean Algebra and Minimization
Question 5 Explanation: 
Given, f=m_0+m_2+m_3+m_5+m_7 and m_1= don't care
Question 6
Which one of the following statements is true about the digital circuit shown in the figure
A
It can be used for dividing the input frequency by 3.
B
It can be used for dividing the input frequency by 5.
C
It can be used for dividing the input frequency by 7.
D
It cannot be reliably used as a frequency divider due to disjoint internal cycles.
GATE EE 2018      Sequential Logic Circuits
Question 6 Explanation: 


So, frequency will be divided by 5.
Question 7
In the logic circuit shown in the figure, Y is given by
A
Y = ABCD
B
Y = (A + B)(C + D)
C
Y = A + B + C + D
D
Y = AB + CD
GATE EE 2018      Logic Gates
Question 7 Explanation: 


Question 8
For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions Q_{A}Q_{B}Q_{C}=Q_{A}'Q_{B}'Q'_{C}=100

The minimum number of clock cycles after which the output Z would again become zero is ________
A
4
B
5
C
6
D
7
GATE EE 2017-SET-2      Sequential Logic Circuits
Question 8 Explanation: 


The output Z will again become zero after 6th clock cycle.
Question 9
For a 3-input logic circuit shown below, the output Z can be expressed as
A
Q+\bar{R}
B
P\bar{Q}+R
C
\bar{Q}+R
D
P+\bar{Q}+R
GATE EE 2017-SET-2      Logic Gates
Question 9 Explanation: 


Z=\overline{\overline{P\bar{Q}}\cdot Q\cdot \overline{Q\cdot R} }
\;\;=P\bar{Q}+\bar{Q}+Q R
\;\;=\bar{Q}(P+1)+QR
\;\;=\bar{Q}+QR
\;\;=(\bar{Q}+Q)(\bar{Q}+R)
\;\;=\bar{Q}+R
Question 10
The logical gate implemented using the circuit shown below where, V_1 \; and \; V_2 are inputs (with 0 V as digital 0 and 5 V as digital 1) and V_{OUT} is the output is
A
NOT
B
NOR
C
NAND
D
XOR
GATE EE 2017-SET-1      Logic Families and Miscellaneous
Question 10 Explanation: 


When V_1= high 5 V, Q_1 on, V_{out}=0
V_2= high 5 V, Q_2 on, V_{out}=0
Thus when any V_1 or V_2 is high then, V_{out}=0

Thus, it is a NOR gate.
There are 10 questions to complete.
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