Digital Electronics

Question 1
The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flipflops, with each flip-flop having a propagation delay of 20 ns, is ___________. (round off to one decimal place)
A
15.5
B
20.4
C
12.5
D
8.6
GATE EE 2022      Sequential Logic Circuits
Question 1 Explanation: 
f_{max}=\frac{1}{nt_p}=\frac{1}{4 \times 20 \times 10^{-9}}=12.50MHz
Question 2
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)
A
5
B
10
C
50
D
25
GATE EE 2022      Sequential Logic Circuits
Question 2 Explanation: 
Overall MOD = 2 x 5 = 10
Question 3
A counter is constructed with three D flip-flops. The input-output pairs are named (D_{0},\:Q_{0}), (D_{1},\:Q_{1}) and (D_{2},\:Q_{2}), where the subscript 0 denotes the least significant bit. The output sequence is desired to be the Gray-code sequence 000, \:001, \:011,\: 010, \:110,\:111,\: 101 and 100, repeating periodically. Note that the bits are listed in the Q_{2}\:Q_{1}\:Q_{0} format. The combinational logic expression for D_{1} is
A
Q_{2}Q_{1}Q_{0}
B
Q_{2}Q_{0}+Q_{1}\overline{Q_{0}}
C
\overline{Q_{2}}Q_{0}+Q_{1}\overline{Q_{0}}
D
Q_{2}Q_{1}+\overline{Q_{2}}\:\overline{Q_{1}}
GATE EE 2021      Combinational Logic Circuits
Question 3 Explanation: 




D_{1}=\bar{Q}_{2} Q_{0}+Q_{1} \bar{Q}_{0}
Question 4
A 16-bit synchronous binary up-counter is clocked with a frequency f_{\text{CLK}}.The two most significant bits are \text{OR-ed} together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is \text{24 ms}. The clock frequency f_{\text{CLK}} is ___________\text{MHz}. (Round off to 2 decimal places.)
A
4.12
B
2.05
C
6.08
D
3.25
GATE EE 2021      Sequential Logic Circuits
Question 4 Explanation: 


y = 1 for 24 m sec
\begin{array}{llcccc} & & Q_{15} & Q_{14} & \ldots \ldots & Q_{0} \\ y=1 & \text { Starts at } & 0100 & 0000 & 0000 & 0000 \\ y=1 & \text { Ends at } & 1111 & 1111 & 1111 & 1111 \end{array}
Total number of states for which y=1 is 2^{16}-2^{14}
\begin{aligned} \text { Time is }\left(2^{16}-2^{14}\right) T &=24 \mathrm{msec} \\ f &=\frac{1}{T}=2.05 \mathrm{MHz} \end{aligned}
Question 5
An 8085 microprocessor accesses two memory locations (2001 H) and (2002H), that contain 8-bit numbers 98H and B1H respectively. The following program is executed:

LXI H, 2001 H
MVIA, 21H
INX H
ADD M
INX H
MOV M, A
HLT

At the end of this program, the memory location 2003H contains the number in decimal (base 10) form ________
A
200
B
21
C
210
D
221
GATE EE 2020      Microprocessors
Question 5 Explanation: 
\begin{aligned} LXI H, 2001 H & \rightarrow [HL] \rightarrow 2001 H \\MVI A, 21 H & \rightarrow [A] \leftarrow 21 H \\INX H & \rightarrow [HL] \rightarrow 2002 H \\ ADD M & \rightarrow [A] + [2002] \rightarrow [A] \\ &= (21H + B1 H) \rightarrow [A] \\ &= D2 H \rightarrow [A] \\ INX H & \rightarrow [HL] \rightarrow 2003 H \\ MOV M, A & \rightarrow [2003] \leftarrow [A] \\ [2003] &= D2 H = (1101\; 0010)_2 \\ &= 1 \times 2^7+1\times 2^6+1\times 2^4 +1\times 2^1 \\&= 128 + 64 + 16 + 2 \\&= 210 \end{aligned}
Question 6
A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0):

what is the output of this detector?
A
1,1,0,0,0,0,1,1,0,1,0,0
B
0,1,0,0,0,0,0,1,0,1,0,0
C
0,1,0,0,0,0,0,1,0,1,1,0
D
0,1,0,0,0,0,0,0,1,0,0,0
GATE EE 2020      Sequential Logic Circuits
Question 6 Explanation: 
Given overlapping sequence input data = 11010011010110
It will give output 1 when 101 is detected.
\begin{aligned} 110 - 0\\ 101 - 1\\ 010 - 0\\ 100 - 0\\ 001 - 0\\ 011 - 0\\ 110 - 0\\ 101 - 1\\ 010 - 0\\ 101 - 1\\ 011 - 0\\ 110 - 0\\ \end{aligned}
So, output = 010000010100
Question 7
In the circuit shown below, X and Y are digital inputs, and Z is a digital output. The equivalent circuit is a
A
NAND gate
B
NOR gate
C
XOR gate
D
XNOR gate
GATE EE 2019      Logic Gates
Question 7 Explanation: 
The Boolean expression for the output of the digital circuit is shown below

The above expression is of XOR gate.
Question 8
The output expression for the Karnaugh map shown below is
A
Q\bar{R}+S
B
Q\bar{R}+\bar{S}
C
QR+S
D
QR+\bar{S}
GATE EE 2019      Boolean Algebra and Minimization
Question 8 Explanation: 


Output=Q\bar{R}+S
Question 9
Digital input signals A,B,C with A as the MSB and C as the LSB are used to realize the Boolean function
F=m_{0}+m_{2}+m_{3}+m_{5}+m_{7}, \; where \; m_{i}
denotes the i^{th} minterm. In addition, F has a don't care for m_1. The simplified expression for F is given by
A
\bar{A}\bar{C}+\bar{B}C+AC
B
\bar{A}+C
C
\bar{C}+A
D
\bar{A}C+BC+A\bar{C}
GATE EE 2018      Boolean Algebra and Minimization
Question 9 Explanation: 
Given, f=m_0+m_2+m_3+m_5+m_7 and m_1= don't care
Question 10
Which one of the following statements is true about the digital circuit shown in the figure
A
It can be used for dividing the input frequency by 3.
B
It can be used for dividing the input frequency by 5.
C
It can be used for dividing the input frequency by 7.
D
It cannot be reliably used as a frequency divider due to disjoint internal cycles.
GATE EE 2018      Sequential Logic Circuits
Question 10 Explanation: 


So, frequency will be divided by 5.
There are 10 questions to complete.