Question 1 |

The logical gate implemented using the circuit shown below where, V_1 \; and \; V_2 are inputs (with
0 V as digital 0 and 5 V as digital 1) and V_{OUT} is the output is

NOT | |

NOR | |

NAND | |

XOR |

Question 1 Explanation:

When V_1= high 5 V, Q_1 on, V_{out}=0

V_2= high 5 V, Q_2 on, V_{out}=0

Thus when any V_1 or V_2 is high then, V_{out}=0

Thus, it is a NOR gate.

Question 2 |

In the circuit shown below, Q_{1} has negligible collector-to-emitter saturation
voltage and the diode drops negligible voltage across it under forward bias. If V_{cc}
is +5 V, X and Y are digital signals with 0 V as logic 0 and V_{cc} as logic 1, then
the Boolean expression for Z is

XY | |

\bar{X}Y | |

X\bar{Y} | |

\overline{XY} |

Question 2 Explanation:

\Rightarrow \;\;Z=\bar{X}Y

Question 3 |

The TTL circuit shown in the figure is fed with the waveform X (also shown).
All gates have equal propagation delay of 10 ns. The output Y of the circuit is

A | |

B | |

C | |

D |

Question 3 Explanation:

Question 4 |

A TTL NOT gate circuit is shown in figure. Assuming V_{BE}=0.7 V of both the
transistors, if V_{i}=3.0 V, then the states of the two transistors will be

Q_{1} ON and Q_{2} OFF | |

Q_{1} reverse ON and Q_{2} OFF | |

Q_{1} reverse ON and Q_{2} ON | |

Q_{1} OFF and Q_{2} reverse ON |

Question 4 Explanation:

When V_i=3 V then Q_1 will be in reverse active mode i.e. reverse ON and Q_2 will be ON.

Question 5 |

If X_{1} and X_{2} are the inputs to the circuit shown in the figure, the output Q is

\overline{X_{1} + X_{2}} | |

\overline{X_{1}\cdot X_{2}} | |

\overline{X_{1}}\cdot X_{2} | |

\overline{X_{2}}\cdot X_{1} |

Question 5 Explanation:

Y_1=\bar{X_1}

Output, Q=\overline{Y_1+X_2}=\overline{(\bar{X_1}+X_2)}

Q=X_1\cdot \bar{X_2}

Output, Q=\overline{Y_1+X_2}=\overline{(\bar{X_1}+X_2)}

Q=X_1\cdot \bar{X_2}

There are 5 questions to complete.