Question 1 |
In a given 8-bit general purpose micro-controller there are following flags.
C-Carry, A-Auxiliary Carry, O-Overflow flag, PParity ( 0 for even, 1 for odd) R0 and R 1 are the two general purpose registers of the microcontroller.
After execution of the following instructions, the decimal equivalent of the binary sequence of the flag pattern [CAOP] will be
MOV R0, +0x60
MOV R1, +0x46
ADD R0, R 1
C-Carry, A-Auxiliary Carry, O-Overflow flag, PParity ( 0 for even, 1 for odd) R0 and R 1 are the two general purpose registers of the microcontroller.
After execution of the following instructions, the decimal equivalent of the binary sequence of the flag pattern [CAOP] will be
MOV R0, +0x60
MOV R1, +0x46
ADD R0, R 1
1 | |
2 | |
3 | |
7 |
Question 1 Explanation:
MOV R_{0},+0 \times 60 \Rightarrow R_{0} \leftarrow 60 \mathrm{H}
MOV R_{1},+0 \times 46 \Rightarrow \mathrm{R}_{1} \leftarrow 46 \mathrm{H}
ADD R_{0}, R_{1} :
\begin{array}{lllllllll} 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & \rightarrow 46 \mathrm{H} \\ \hline 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & \rightarrow \mathrm{A} 6 \mathrm{H} \\ \hline \end{array}
Now, carry flag (C Y)=0
Auxiliary carry (\mathrm{AC})=0
\left[\because\right. No carry fro D_{3} to \left.D_{4}\right]
\because \mathrm{MSB}=1, overflow flag =1
P=0[\because Four 1's i.e. even numb
er ] \therefore Required Flag patter =[ CAOP ]
=[0010]_{2}=2
MOV R_{1},+0 \times 46 \Rightarrow \mathrm{R}_{1} \leftarrow 46 \mathrm{H}
ADD R_{0}, R_{1} :
\begin{array}{lllllllll} 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & \rightarrow 46 \mathrm{H} \\ \hline 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & \rightarrow \mathrm{A} 6 \mathrm{H} \\ \hline \end{array}
Now, carry flag (C Y)=0
Auxiliary carry (\mathrm{AC})=0
\left[\because\right. No carry fro D_{3} to \left.D_{4}\right]
\because \mathrm{MSB}=1, overflow flag =1
P=0[\because Four 1's i.e. even numb
er ] \therefore Required Flag patter =[ CAOP ]
=[0010]_{2}=2
Question 2 |
An 8085 microprocessor accesses two memory locations (2001 H) and (2002H), that
contain 8-bit numbers 98H and B1H respectively. The following program is executed:
LXI H, 2001 H
MVIA, 21H
INX H
ADD M
INX H
MOV M, A
HLT
At the end of this program, the memory location 2003H contains the number in decimal (base 10) form ________
LXI H, 2001 H
MVIA, 21H
INX H
ADD M
INX H
MOV M, A
HLT
At the end of this program, the memory location 2003H contains the number in decimal (base 10) form ________
200 | |
21 | |
210 | |
221 |
Question 2 Explanation:
\begin{aligned} LXI H, 2001 H & \rightarrow [HL] \rightarrow 2001 H \\MVI A, 21 H & \rightarrow [A] \leftarrow 21 H \\INX H & \rightarrow [HL] \rightarrow 2002 H \\ ADD M & \rightarrow [A] + [2002] \rightarrow [A] \\ &= (21H + B1 H) \rightarrow [A] \\ &= D2 H \rightarrow [A] \\ INX H & \rightarrow [HL] \rightarrow 2003 H \\ MOV M, A & \rightarrow [2003] \leftarrow [A] \\ [2003] &= D2 H = (1101\; 0010)_2 \\ &= 1 \times 2^7+1\times 2^6+1\times 2^4 +1\times 2^1 \\&= 128 + 64 + 16 + 2 \\&= 210 \end{aligned}
Question 3 |
In 8085A microprocessor, the operation performed by the instruction LHLD 2100H is
(H)\leftarrow 21_{H},(L) \leftarrow 00_{H} | |
(H)\leftarrow M(2100_{H}),(L) \leftarrow M(2101_{H}) | |
(H)\leftarrow M(2101_{H}),(L) \leftarrow M(2100_{H}) | |
(H)\leftarrow 00_{H},(L) \leftarrow 21_{H} |
Question 4 |
In an 8085 microprocessor, the following program is executed
At the end of program, register A contains
At the end of program, register A contains
60H | |
30H | |
06H | |
03H |
Question 4 Explanation:
For the RAR operation
and B\leftarrow 04
Similarly for each RAR operation the content of B is decremented by '1' till it becomes 00H. Thus,
B\leftarrow 04\;\; A\leftarrow 00000011
B\leftarrow 03\;\; A\leftarrow 10000001
B\leftarrow 02\;\; A\leftarrow 11000000
B\leftarrow 01\;\; A\leftarrow 01100000 B\leftarrow 00
Therefore, at the end of the program, egister 'A' contains 60H.
Question 5 |
An output device is interfaced with 8-bit microprocessor 8085A. The interfacing
circuit is shown in figure
The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enables lines E_1,\bar{E_2},\bar{E_3}. The address of the device is
The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enables lines E_1,\bar{E_2},\bar{E_3}. The address of the device is
50_H | |
5000_H | |
A0_H | |
A000_H |
Question 5 Explanation:
For the given decoder
E-=A_{12}\bar{A_{11}}=1 (enable)
\therefore \;\; A_{12} should be HIGH and A_{11} should be LOW.
Also, E_2=E_3=0(disable)
The decoder output depends on I_2=A_{15}, I_1=A_{14} and I_0=A_{13} which should be 010 respectively to enable the output port.
The address of the device is 5000H-57FFH,
E-=A_{12}\bar{A_{11}}=1 (enable)
\therefore \;\; A_{12} should be HIGH and A_{11} should be LOW.
Also, E_2=E_3=0(disable)
The decoder output depends on I_2=A_{15}, I_1=A_{14} and I_0=A_{13} which should be 010 respectively to enable the output port.
The address of the device is 5000H-57FFH,
There are 5 questions to complete.