Microprocessors

Question 1
An 8085 microprocessor accesses two memory locations (2001 H) and (2002H), that contain 8-bit numbers 98H and B1H respectively. The following program is executed:

LXI H, 2001 H
MVIA, 21H
INX H
ADD M
INX H
MOV M, A
HLT

At the end of this program, the memory location 2003H contains the number in decimal (base 10) form ________
A
200
B
21
C
210
D
221
GATE EE 2020   Digital Electronics
Question 1 Explanation: 
\begin{aligned} LXI H, 2001 H & \rightarrow [HL] \rightarrow 2001 H \\MVI A, 21 H & \rightarrow [A] \leftarrow 21 H \\INX H & \rightarrow [HL] \rightarrow 2002 H \\ ADD M & \rightarrow [A] + [2002] \rightarrow [A] \\ &= (21H + B1 H) \rightarrow [A] \\ &= D2 H \rightarrow [A] \\ INX H & \rightarrow [HL] \rightarrow 2003 H \\ MOV M, A & \rightarrow [2003] \leftarrow [A] \\ [2003] &= D2 H = (1101\; 0010)_2 \\ &= 1 \times 2^7+1\times 2^6+1\times 2^4 +1\times 2^1 \\&= 128 + 64 + 16 + 2 \\&= 210 \end{aligned}
Question 2
In 8085A microprocessor, the operation performed by the instruction LHLD 2100H is
A
(H)\leftarrow 21_{H},(L) \leftarrow 00_{H}
B
(H)\leftarrow M(2100_{H}),(L) \leftarrow M(2101_{H})
C
(H)\leftarrow M(2101_{H}),(L) \leftarrow M(2100_{H})
D
(H)\leftarrow 00_{H},(L) \leftarrow 21_{H}
GATE EE 2014-SET-3   Digital Electronics
Question 3
In an 8085 microprocessor, the following program is executed

At the end of program, register A contains
A
60H
B
30H
C
06H
D
03H
GATE EE 2014-SET-2   Digital Electronics
Question 3 Explanation: 


For the RAR operation

and B\leftarrow 04
Similarly for each RAR operation the content of B is decremented by '1' till it becomes 00H. Thus,
B\leftarrow 04\;\; A\leftarrow 00000011
B\leftarrow 03\;\; A\leftarrow 10000001
B\leftarrow 02\;\; A\leftarrow 11000000
B\leftarrow 01\;\; A\leftarrow 01100000 B\leftarrow 00
Therefore, at the end of the program, egister 'A' contains 60H.
Question 4
An output device is interfaced with 8-bit microprocessor 8085A. The interfacing circuit is shown in figure

The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enables lines E_1,\bar{E_2},\bar{E_3}. The address of the device is
A
50_H
B
5000_H
C
A0_H
D
A000_H
GATE EE 2014-SET-1   Digital Electronics
Question 4 Explanation: 
For the given decoder
E-=A_{12}\bar{A_{11}}=1 (enable)
\therefore \;\; A_{12} should be HIGH and A_{11} should be LOW.
Also, E_2=E_3=0(disable)
The decoder output depends on I_2=A_{15}, I_1=A_{14} and I_0=A_{13} which should be 010 respectively to enable the output port.

The address of the device is 5000H-57FFH,
Question 5
A portion of the main program to call a subroutine SUB in an 8085 environment is given below.
:
:
     LXI D, DISP
LP : CALL SUB
:
:
It is desired that control be returned to LP+DISP+3 when the RET instruction is executed in the subroutine. The set of instructions that precede the RET instruction in the subroutine are
A
A
B
B
C
C
D
D
GATE EE 2011   Digital Electronics
Question 5 Explanation: 
Call takes 3 address locations, RET always returns to LP+3 location, this stored in SP.
So to return to LP+DISP+3.
We have to add DISP to SP.
POP H
DAD D
PUSH H
Normal call operation shown.
Question 6
When a "CALL Addr" instruction is executed, the CPU carries out the following sequential operations internally :

Note: (R) means content of register R
((R)) means content of memory location pointed to by R.
PC means Program Counter
SP means Stack Pointer

A
A
B
B
C
C
D
D
GATE EE 2010   Digital Electronics
Question 6 Explanation: 
First of all content of PC is loaded into stack i.e. address of next instruction to be executed is loaded onto stack. i.e. SP is decremented then PC is loaded by address given in call instruction.
Question 7
In an 8085 microprocessor, the contents of the Accumulator, after the following instructions are executed will become

XRA A
MVI B, F0 H
SUB B
A
01 H
B
0F H
C
F0 H
D
10 H
GATE EE 2009   Digital Electronics
Question 8
The increasing order of speed of data access for the following device is

(I) Cache Memory
(II) CD-ROM
(III) Dynamic RAM
(IV) Processor Registers
(V) Magnetic Tape
A
(V), (II), (III), (IV), (I)
B
(V), (II), (III), (I), (IV)
C
(II), (I), (III), (IV), (V)
D
(V), (II), (I), (III), (IV)
GATE EE 2009   Digital Electronics
Question 8 Explanation: 
Access time of the residter is very less than that from a memory access. So speed of data access is faster in case of processor register.
Second highest is cache memory because it's size is small, so searching of data takes less time.
Question 9
The content of some of the memory location in an 8085 accumulator based system are given below

The content of stack (SP), program counter (PC) and (H,L) are 2700H, 2100H and 0000H respectively. When the following sequence of instruction are executed.

2100 H: DAD SP
2101 H: PCHL

the content of (SP) and (PC) at the end of execution will be
A
PC = 2102H, SP = 2700H
B
PC = 2700H, SP = 2700H
C
PC = 2800H, SP = 26FEH
D
PC = 2A02H, SP = 2702H
GATE EE 2008   Digital Electronics
Question 9 Explanation: 
Given,
(SP) = 2700H
(PC)=2100H
(HL)=0000H
2100H : DAD SP
(SP) +(HL) \rightarrow (HL)
2700H +0000H =2700H stored in HL pair.
2101H : PCHL : the content of HL are transferred to (PC)
So, now (PC) =2700H and (SP) also unchanged
(PC)=2700H
(SP)=2700H
Question 10
An input device is interfaced with Intel 8085A microprocessor as memory mapped I/O. The address of the device is 2500H. In order to input data from the device to accumulator, the sequence of instructions will be
A
LXI H, 2500H
MOV A, M
B
LXI H, 2500H
MOV M, A
C
LHLD 2500H
MOV A, M
D
LHLD 2500H
MOV M, A
GATE EE 2008   Digital Electronics
There are 10 questions to complete.
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