Sequential Logic Circuits

Question 1
A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0):

what is the output of this detector?
A
1,1,0,0,0,0,1,1,0,1,0,0
B
0,1,0,0,0,0,0,1,0,1,0,0
C
0,1,0,0,0,0,0,1,0,1,1,0
D
0,1,0,0,0,0,0,0,1,0,0,0
GATE EE 2020   Digital Electronics
Question 1 Explanation: 
Given overlapping sequence input data = 11010011010110
It will give output 1 when 101 is detected.
\begin{aligned} 110 - 0\\ 101 - 1\\ 010 - 0\\ 100 - 0\\ 001 - 0\\ 011 - 0\\ 110 - 0\\ 101 - 1\\ 010 - 0\\ 101 - 1\\ 011 - 0\\ 110 - 0\\ \end{aligned}
So, output = 010000010100
Question 2
Which one of the following statements is true about the digital circuit shown in the figure
A
It can be used for dividing the input frequency by 3.
B
It can be used for dividing the input frequency by 5.
C
It can be used for dividing the input frequency by 7.
D
It cannot be reliably used as a frequency divider due to disjoint internal cycles.
GATE EE 2018   Digital Electronics
Question 2 Explanation: 


So, frequency will be divided by 5.
Question 3
For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions Q_{A}Q_{B}Q_{C}=Q_{A}'Q_{B}'Q'_{C}=100

The minimum number of clock cycles after which the output Z would again become zero is ________
A
4
B
5
C
6
D
7
GATE EE 2017-SET-2   Digital Electronics
Question 3 Explanation: 


The output Z will again become zero after 6th clock cycle.
Question 4
The current state Q_{A}Q_{B} of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is
A
00
B
01
C
11
D
10
GATE EE 2016-SET-1   Digital Electronics
Question 4 Explanation: 
From the figure we get
J_A=K_A=1
J_B=K_B=\bar{Q_A}

So, next state will be 11.
Question 5
In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is Q_{1}Q_{0}=00. The state (Q_{1}Q_{0}), immediately after the 333^{rd} clock pulse is
A
00
B
01
C
10
D
11
GATE EE 2015-SET-2   Digital Electronics
Question 5 Explanation: 
From the circuit, we can find out that
J_0=Q'_1,\;K_0=Q_1
J_1=Q_0,\;K_1=Q'_0

So state diagram is

at every 4th clock, the system is at 00
So, at 332 it will be at 00
So, at 333 clock it will be at 01.
Question 6
The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of Q_{2}Q_{1}Q_{0}=000. This state Q_{2}Q_{1}Q_{0}=000 will repeat after _______ number of cycles of the clock CLK
A
4
B
5
C
6
D
7
GATE EE 2015-SET-1   Digital Electronics
Question 6 Explanation: 
JK flip-flop1 and 2 from a syncgronous sequential circuits and they are synchronized with the output of 0th JK flip-flop.

Number of cycles = 3 i.e. equal to 6 clock cycles.
Question 7
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don't care condition, and Q is the output representing the state. The logic gate represented by the state diagram is
A
XOR
B
OR
C
AND
D
NAND
GATE EE 2014-SET-3   Digital Electronics
Question 7 Explanation: 


If any one of the input is zero, output is 1 and for both inputs as '1' , output is '0', which represents the NAND gate.
Question 8
A JK flip flop can be implemented by T flip-flops. Identify the correct implementation.
A
A
B
B
C
C
D
D
GATE EE 2014-SET-2   Digital Electronics
Question 8 Explanation: 
To obtain a JK flip-flop from a T flip-flop, we first constuct the characteristic table of JK flip-flop, and then obtain the excitation values for the T flip-flop as shown below

Now, assuming T to be an output, we solve it in terms of J, K, Q_n inputs. This gives the defination of the logic to be applied on the T input.
Also, observing the given options, we solve for T using a maxterms map instead of using a minterms map, as shown below

T=(J+Q_n)\cdot (K+\bar{Q_n})
The circuit corresponding to this expression is given in option (B).
Question 9
A cascade of three identical modulo-5 counters has an overall modulus of
A
5
B
25
C
125
D
625
GATE EE 2014-SET-1   Digital Electronics
Question 9 Explanation: 
Overall modulus =5 x 5 x 5=125
Question 10
The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is '0', then the frequency of the output waveform Q in kHz is
A
0.25
B
0.5
C
1
D
2
GATE EE 2013   Digital Electronics
Question 10 Explanation: 
x=\overline{(Q\oplus \bar{Q})\cdot (Q \odot \bar{Q})}
\;\;=\overline{1\cdot 0}=1
\because \;\; X=1=T \Rightarrow Q always toggle whenever clock triggers.

\therefore \; f_Q=\frac{f_{clk}}{2}=\frac{1kHz}{2}=0.5kHz
There are 10 questions to complete.
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