Sequential Logic Circuits

Question 1
The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flipflops, with each flip-flop having a propagation delay of 20 ns, is ___________. (round off to one decimal place)
A
15.5
B
20.4
C
12.5
D
8.6
GATE EE 2022   Digital Electronics
Question 1 Explanation: 
f_{max}=\frac{1}{nt_p}=\frac{1}{4 \times 20 \times 10^{-9}}=12.50MHz
Question 2
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)
A
5
B
10
C
50
D
25
GATE EE 2022   Digital Electronics
Question 2 Explanation: 
Overall MOD = 2 x 5 = 10
Question 3
A 16-bit synchronous binary up-counter is clocked with a frequency f_{\text{CLK}}.The two most significant bits are \text{OR-ed} together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is \text{24 ms}. The clock frequency f_{\text{CLK}} is ___________\text{MHz}. (Round off to 2 decimal places.)
A
4.12
B
2.05
C
6.08
D
3.25
GATE EE 2021   Digital Electronics
Question 3 Explanation: 


y = 1 for 24 m sec
\begin{array}{llcccc} & & Q_{15} & Q_{14} & \ldots \ldots & Q_{0} \\ y=1 & \text { Starts at } & 0100 & 0000 & 0000 & 0000 \\ y=1 & \text { Ends at } & 1111 & 1111 & 1111 & 1111 \end{array}
Total number of states for which y=1 is 2^{16}-2^{14}
\begin{aligned} \text { Time is }\left(2^{16}-2^{14}\right) T &=24 \mathrm{msec} \\ f &=\frac{1}{T}=2.05 \mathrm{MHz} \end{aligned}
Question 4
A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0):

what is the output of this detector?
A
1,1,0,0,0,0,1,1,0,1,0,0
B
0,1,0,0,0,0,0,1,0,1,0,0
C
0,1,0,0,0,0,0,1,0,1,1,0
D
0,1,0,0,0,0,0,0,1,0,0,0
GATE EE 2020   Digital Electronics
Question 4 Explanation: 
Given overlapping sequence input data = 11010011010110
It will give output 1 when 101 is detected.
\begin{aligned} 110 - 0\\ 101 - 1\\ 010 - 0\\ 100 - 0\\ 001 - 0\\ 011 - 0\\ 110 - 0\\ 101 - 1\\ 010 - 0\\ 101 - 1\\ 011 - 0\\ 110 - 0\\ \end{aligned}
So, output = 010000010100
Question 5
Which one of the following statements is true about the digital circuit shown in the figure
A
It can be used for dividing the input frequency by 3.
B
It can be used for dividing the input frequency by 5.
C
It can be used for dividing the input frequency by 7.
D
It cannot be reliably used as a frequency divider due to disjoint internal cycles.
GATE EE 2018   Digital Electronics
Question 5 Explanation: 


So, frequency will be divided by 5.
Question 6
For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions Q_{A}Q_{B}Q_{C}=Q_{A}'Q_{B}'Q'_{C}=100

The minimum number of clock cycles after which the output Z would again become zero is ________
A
4
B
5
C
6
D
7
GATE EE 2017-SET-2   Digital Electronics
Question 6 Explanation: 


The output Z will again become zero after 6th clock cycle.
Question 7
The current state Q_{A}Q_{B} of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is
A
00
B
01
C
11
D
10
GATE EE 2016-SET-1   Digital Electronics
Question 7 Explanation: 
From the figure we get
J_A=K_A=1
J_B=K_B=\bar{Q_A}

So, next state will be 11.
Question 8
In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is Q_{1}Q_{0}=00. The state (Q_{1}Q_{0}), immediately after the 333^{rd} clock pulse is
A
00
B
01
C
10
D
11
GATE EE 2015-SET-2   Digital Electronics
Question 8 Explanation: 
From the circuit, we can find out that
J_0=Q'_1,\;K_0=Q_1
J_1=Q_0,\;K_1=Q'_0

So state diagram is

at every 4th clock, the system is at 00
So, at 332 it will be at 00
So, at 333 clock it will be at 01.
Question 9
The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of Q_{2}Q_{1}Q_{0}=000. This state Q_{2}Q_{1}Q_{0}=000 will repeat after _______ number of cycles of the clock CLK
A
4
B
5
C
6
D
7
GATE EE 2015-SET-1   Digital Electronics
Question 9 Explanation: 
JK flip-flop1 and 2 from a syncgronous sequential circuits and they are synchronized with the output of 0th JK flip-flop.

Number of cycles = 3 i.e. equal to 6 clock cycles.
Question 10
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don't care condition, and Q is the output representing the state. The logic gate represented by the state diagram is
A
XOR
B
OR
C
AND
D
NAND
GATE EE 2014-SET-3   Digital Electronics
Question 10 Explanation: 


If any one of the input is zero, output is 1 and for both inputs as '1' , output is '0', which represents the NAND gate.
There are 10 questions to complete.