# Sequential Logic Circuits

 Question 1
Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is

 A 4 B 8 C 16 D 32
GATE EE 2023   Digital Electronics
Question 1 Explanation:
Redraw the circuit :

From circuit :
$\begin{array}{c|ccc|cccc} & & & &\overline{\mathrm{Q}_{2}} & \mathrm{Q}_{2} & \overline{\mathrm{Q}}_{1} & \mathrm{Q}_{1} \oplus \mathrm{Q}_{2} \\ \mathrm{CLK} & \mathrm{D} & \mathrm{Q}_{1} & \mathrm{Q}_{0} & \mathrm{~A} & \mathrm{~B} & \mathrm{C} & \mathrm{D} \\ \hline 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 2 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ \hline \end{array}$
$\therefore \quad A B C D=(1000)_{2}=(8)_{10}$
 Question 2
The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flipflops, with each flip-flop having a propagation delay of 20 ns, is ___________. (round off to one decimal place)
 A 15.5 B 20.4 C 12.5 D 8.6
GATE EE 2022   Digital Electronics
Question 2 Explanation:
$f_{max}=\frac{1}{nt_p}=\frac{1}{4 \times 20 \times 10^{-9}}=12.50MHz$

 Question 3
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)
 A 5 B 10 C 50 D 25
GATE EE 2022   Digital Electronics
Question 3 Explanation:
Overall MOD = 2 x 5 = 10
 Question 4
A 16-bit synchronous binary up-counter is clocked with a frequency $f_{\text{CLK}}$.The two most significant bits are $\text{OR-ed}$ together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is $\text{24 ms}$. The clock frequency $f_{\text{CLK}}$ is ___________$\text{MHz}$. (Round off to 2 decimal places.)
 A 4.12 B 2.05 C 6.08 D 3.25
GATE EE 2021   Digital Electronics
Question 4 Explanation:

$y = 1$ for 24 m sec
$\begin{array}{llcccc} & & Q_{15} & Q_{14} & \ldots \ldots & Q_{0} \\ y=1 & \text { Starts at } & 0100 & 0000 & 0000 & 0000 \\ y=1 & \text { Ends at } & 1111 & 1111 & 1111 & 1111 \end{array}$
Total number of states for which $y=1$ is $2^{16}-2^{14}$
\begin{aligned} \text { Time is }\left(2^{16}-2^{14}\right) T &=24 \mathrm{msec} \\ f &=\frac{1}{T}=2.05 \mathrm{MHz} \end{aligned}
 Question 5
A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0):

what is the output of this detector?
 A 1,1,0,0,0,0,1,1,0,1,0,0 B 0,1,0,0,0,0,0,1,0,1,0,0 C 0,1,0,0,0,0,0,1,0,1,1,0 D 0,1,0,0,0,0,0,0,1,0,0,0
GATE EE 2020   Digital Electronics
Question 5 Explanation:
Given overlapping sequence input data $= 11010011010110$
It will give output $1$ when $101$ is detected.
\begin{aligned} 110 - 0\\ 101 - 1\\ 010 - 0\\ 100 - 0\\ 001 - 0\\ 011 - 0\\ 110 - 0\\ 101 - 1\\ 010 - 0\\ 101 - 1\\ 011 - 0\\ 110 - 0\\ \end{aligned}
So, output $= 010000010100$

There are 5 questions to complete.